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41. 发明申请

US20060146786A1 Implementation of the intelligent network in the next generation networks and its interconnection to the pstn 有权
标题翻译：智能网在下一代网络中的实现及其与pstn的互连
公开(公告)号：US20060146786A1
公开(公告)日：2006-07-06
申请号：US10537043
申请日：2002-12-03
申请人： Weiliang Lian , Aijun Li , Yimin Xi , Lei Guo
发明人： Weiliang Lian , Aijun Li , Yimin Xi , Lei Guo
IPC分类号： H04L12/66
CPC分类号： H04Q3/0045 , H04L12/66 , H04Q3/0029
摘要： The present invention discloses a Softswitch and system for implementing the intelligent network in the next generation networks and a method for interconnecting the intelligent networks to the PSTN. The Softswitch comprises: a network adaptive device for implementing the communication between the Softswitch and other devices in said network, as well as receiving the call request; a call server for determining whether the call received by said network adaptive device is a common call or the call of the intelligent network and processing the common call; and an INAP adapter for responding the call of the intelligent network and encoding/decoding the INAP message.
摘要翻译：本发明公开了一种用于在下一代网络中实现智能网的软交换机和系统，以及将智能网与PSTN互连的方法。软交换机包括：网络自适应设备，用于实现软交换与所述网络中的其他设备之间的通信，以及接收呼叫请求; 呼叫服务器，用于确定由所述网络自适应设备接收的呼叫是公共呼叫还是智能网络的呼叫并处理公共呼叫; 以及用于响应智能网络的呼叫并对INAP消息进行编码/解码的INAP适配器。

42. 外观设计

USD949816S1 Baby monitor 有权
公开(公告)号：USD949816S1
公开(公告)日：2022-04-26
申请号：US29747801
申请日：2020-08-25
申请人： Lei Guo
设计人： Lei Guo

43. 外观设计

USD759389S1 Showcase 有权
公开(公告)号：USD759389S1
公开(公告)日：2016-06-21
申请号：US29495216
申请日：2014-06-27
申请人： Cheng Li , Lei Guo
设计人： Cheng Li , Lei Guo

44. 发明授权

US09341837B2 Wide field of view foveal night vision systems 有权
标题翻译：广视野中央凹夜视系统
公开(公告)号：US09341837B2
公开(公告)日：2016-05-17
申请号：US14020223
申请日：2013-09-06
申请人： Le Li , Haiping Yu , Lei Guo , Yongxin Tang , Shenggang Wang , Aaron B. Cole
发明人： Le Li , Haiping Yu , Lei Guo , Yongxin Tang , Shenggang Wang , Aaron B. Cole
IPC分类号： G02B23/00 , G02B23/12
CPC分类号： G02B23/12 , G02B23/125 , G02B23/18
摘要： An optical viewing apparatus may include an objective lens assembly and an one eye piece assembly connected to the objective lens assembly. The optical viewing apparatus may exhibit a field of view in the range of between 40° and, preferably beyond 80°, and an eye-relief of at least 15 mm, and the optical viewing apparatus may exhibit a foveated image for at least one field of view (FOV) wherein the optical on-axis resolution decays toward the periphery of the field of view.
摘要翻译：光学观察装置可以包括物镜组件和连接到物镜组件的一个眼件组件。光学观察装置可以在40°，优选地超过80°的范围内展现视野，并且可以呈现至少15mm的眼睛浮雕，并且光学观察装置可以呈现至少一个场的移动图像（FOV），其中光轴上分辨率衰减到视场的周边。

45. 发明授权

US09312427B2 Semiconductor structure and method for forming the same 有权
标题翻译：半导体结构及其形成方法
公开(公告)号：US09312427B2
公开(公告)日：2016-04-12
申请号：US14362079
申请日：2012-11-15
申请人： Yuan Li , Lei Guo
发明人： Yuan Li , Lei Guo
IPC分类号： H01L29/06 , H01L33/00 , H01L33/16 , H01L33/20
CPC分类号： H01L33/0062 , H01L33/007 , H01L33/16 , H01L33/20
摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a substrate (100); and a plurality of zigzag structures (200) formed on a surface of the substrate (100), in which each zigzag structure (200) has a first long side (202) and a first short side (204), the first long side (202) of one zigzag structure (200) is adjacent to the first short side (204) of another zigzag structure (200) adjacent to the one zigzag structure (200), each first long side (202) defines a first surface (300) of each zigzag structure (200), each first short side (204) defines a second surface (302) of each zigzag structure, and each first surface (300) is a growth surface for a compound semiconductor layer.
摘要翻译：提供半导体结构及其形成方法。半导体结构包括：衬底（100）; 以及形成在所述基板（100）的表面上的多个锯齿形结构（200），其中每个锯齿形结构（200）具有第一长边（202）和第一短边（204），所述第一长边一个之字形结构（200）的第一表面（202）与邻近一个之字形结构（200）的另一个锯齿形结构（200）的第一短边（204）相邻，每个第一长边（202）限定第一表面（300）每个Z字形结构（200）的每个第一短边（204）限定每个锯齿形结构的第二表面（302），并且每个第一表面（300）是化合物半导体层的生长表面。

46. 发明授权

US09203751B2 IP fragmentation in GTP tunnel 有权
标题翻译： GTP隧道中的IP分片
公开(公告)号：US09203751B2
公开(公告)日：2015-12-01
申请号：US13996231
申请日：2010-12-21
申请人： Wei Gu , Lei Guo , Xiao Li , Di Liu , Lirong Sun , Qi Xia
发明人： Wei Gu , Lei Guo , Xiao Li , Di Liu , Lirong Sun , Qi Xia
IPC分类号： H04L12/28 , H04L12/56 , H04L12/741 , H04W28/06 , H04W76/02 , H04W80/04 , H04L12/805
CPC分类号： H04L45/74 , H04L47/36 , H04W28/06 , H04W76/12 , H04W80/04
摘要： The present invention relates to a method for improving IP fragmentation and transmission of user payload between a User Equipment, UE (10), and a Peer Node, PN (14). The payload is transmitted through a transmission path enabled by at least a first (17,18) and a second (17,18) established tunnel, said tunnels connecting a first (11), (13) and a second (11, 13) node in a Packet Core Network, PCN. The method comprises the steps of: The first node (11,13) fragments (19) at least one received payload packet (15) into fragments (16) on the basis of a minimum Maximum Transmission Unit, MTU, for an upper IP layer of the transmission path. The first node (11,13) encapsulates (20) said fragments at the entry of the first tunnel (17, 18). What particularly characterizes the method is that it further comprises a step where the first node (11,13) determines (21) the MTU for the upper IP layer of the transmission path on the basis of an MTU of a lower IP layer of the transmission path and on the basis of the size of at least one additional tunnel header for the encapsulated fragments (16).
摘要翻译：本发明涉及一种用于改善用户设备，UE（10）和对等节点（PN）（14）之间的用户有效载荷的IP分段和传输的方法。有效载荷通过至少第一（17,18）和第二（17,18）建立的隧道启用的传输路径传输，所述隧道连接第一（11），（13）和第二（11,13）分组核心网络中的节点，PCN。该方法包括以下步骤：第一节点（11,13）根据用于上层IP的最小最大传输单元MTU将至少一个接收到的有效载荷分组（15）分段（19）成片段（16）的传输路径。第一节点（11,13）在第一隧道（17,18）的入口处封装（20）所述碎片。该方法的特征在于，其还包括步骤，其中第一节点（11,13）基于传输的较低IP层的MTU来确定（21）传输路径的上层IP的MTU 并且基于用于封装的片段（16）的至少一个附加隧道头部的大小。

47. 发明授权

US08809877B2 Semiconductor voltage transformation structure 有权
标题翻译：半导体电压转换结构
公开(公告)号：US08809877B2
公开(公告)日：2014-08-19
申请号：US13823627
申请日：2012-11-09
申请人： Lei Guo
发明人： Lei Guo
IPC分类号： H01L27/15 , H01L29/26 , H01L31/12 , H01L33/00 , H01L29/06 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L31/125 , H01L31/173
摘要： A semiconductor voltage transformation structure is provided. The semiconductor voltage transformation structure includes: a first electrode layer ; an electricity-to-light conversion layer formed on the first electrode layer; a second electrode layer formed on the electricity-to-light conversion layer; a first isolation layer formed on the second electrode layer; a third electrode layer formed on the first isolation layer; a light-to-electricity conversion layer formed on the third electrode layer; and a fourth electrode layer formed on the light-to-electricity conversion layer, in which the first isolation layer, the second electrode layer and the third electrode layer are transparent to a working light emitted by the electricity-to-light conversion layer.
摘要翻译：提供了半导体电压转换结构。半导体电压转换结构包括：第一电极层; 形成在所述第一电极层上的电 - 光转换层; 形成在所述电光转换层上的第二电极层; 形成在第二电极层上的第一隔离层; 形成在所述第一隔离层上的第三电极层; 形成在所述第三电极层上的光电转换层; 以及形成在光电转换层上的第四电极层，其中第一隔离层，第二电极层和第三电极层对于由电 - 光转换层发射的工作光是透明的。

48. 发明授权

US08786017B2 Strained Ge-on-insulator structure and method for forming the same 有权
标题翻译：应变绝缘体上的结构及其形成方法
公开(公告)号：US08786017B2
公开(公告)日：2014-07-22
申请号：US13263222
申请日：2011-08-25
申请人： Jing Wang , Jun Xu , Lei Guo
发明人： Jing Wang , Jun Xu , Lei Guo
IPC分类号： H01L27/12
CPC分类号： H01L29/78684 , H01L29/7846
摘要： A strained Ge-on-insulator structure is provided, comprising: a silicon substrate, in which an oxide insulating layer is formed on a surface of the silicon substrate; a Ge layer formed on the oxide insulating layer, in which a first passivation layer is formed between the Ge layer and the oxide insulating layer; a gate stack formed on the Ge layer, a channel region formed below the gate stack, and a source and a drain formed on sides of the channel region; and a plurality of shallow trench isolation structures extending into the silicon substrate and filled with an insulating dielectric material to produce a strain in the channel region. Further, a method for forming the strained Ge-on-insulator structure is also provided.
摘要翻译：提供了一种应变绝缘体上的结构，包括：硅衬底，其中在硅衬底的表面上形成氧化物绝缘层; 形成在所述氧化物绝缘层上的Ge层，其中在所述Ge层和所述氧化物绝缘层之间形成第一钝化层; 形成在Ge层上的栅极叠层，形成在栅叠层下方的沟道区，以及形成在沟道区的侧面上的源极和漏极; 以及延伸到硅衬底中并填充有绝缘电介质材料以在沟道区域中产生应变的多个浅沟槽隔离结构。此外，还提供了用于形成应变的绝缘体上Ge的结构的方法。

49. 发明授权

US08772873B2 Ge-on-insulator structure and method for forming the same 有权
标题翻译：绝缘体上的结构及其形成方法
公开(公告)号：US08772873B2
公开(公告)日：2014-07-08
申请号：US13201903
申请日：2011-07-27
申请人： Jing Wang , Jun Xu , Lei Guo
发明人： Jing Wang , Jun Xu , Lei Guo
IPC分类号： H01L27/12 , H01L21/336 , H01L29/786 , H01L21/28 , H01L21/762 , H01L29/66
CPC分类号： H01L29/78684 , H01L21/28255 , H01L21/76256 , H01L29/66742 , H01L29/78603
摘要： A method for forming a Ge-on-insulator structure is provided, comprising steps of: forming a Ge layer (1200) on a substrate (2000); treating a first surface of the Ge layer (1200) to form a first semiconducting metal-germanide passivation layer (1300); bonding the first semiconducting metal-germanide passivation layer (1300) with a silicon substrate (1100), wherein on a surface of the silicon substrate (1100) an oxide insulating layer is formed; and removing the substrate (2000). Further, a Ge-on-insulator structure formed by the method is also provided.
摘要翻译：提供一种形成绝缘体上Ge结构的方法，包括以下步骤：在衬底（2000）上形成Ge层（1200）; 处理所述Ge层（1200）的第一表面以形成第一半导体金属 - 锗化物钝化层（1300）; 将第一半导体金属 - 锗化物钝化层（1300）与硅衬底（1100）接合，其中在所述硅衬底（1100）的表面上形成氧化物绝缘层; 并移除基板（2000）。此外，还提供了通过该方法形成的绝缘体上Ge结构。

50. 发明申请

US20140138741A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME 有权
标题翻译：半导体结构及其形成方法
公开(公告)号：US20140138741A1
公开(公告)日：2014-05-22
申请号：US13376765
申请日：2011-11-11
申请人： Jing Wang , Lei Guo
发明人： Jing Wang , Lei Guo
IPC分类号： H01L29/778 , H01L29/66
CPC分类号： H01L29/778 , H01L21/764 , H01L21/823412 , H01L21/823418 , H01L21/823481 , H01L29/66431
摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a Si substrate (1100); a plurality of convex structures (1200) formed on the Si substrate (1100), in which every two adjacent convex structures (1200) are separated by a cavity in a predetermined pattern, and the cavity between every two adjacent convex structures (1200) is less than 50 nm in width; a first semiconductor film (1300), in which the first semiconductor film (1300) is formed between the every two adjacent convex structures (1200) and connected with tops of the every two adjacent convex structures (1200); a buffer layer (2100) formed on the first semiconductor film (1300); and a high-mobility III-V compound semiconductor layer (2000) formed on the buffer layer (2100).
摘要翻译：提供半导体结构及其形成方法。半导体结构包括：Si衬底（1100）; 形成在Si衬底（1100）上的多个凸起结构（1200），其中每两个相邻凸起结构（1200）以预定图案被空腔隔开，并且每两个相邻凸起结构（1200）之间的空腔是宽度小于50nm; 第一半导体膜（1300），其中第一半导体膜（1300）形成在每两个相邻的凸起结构（1200）之间并与每两个相邻凸起结构（1200）的顶部连接; 形成在所述第一半导体膜（1300）上的缓冲层（2100）; 和形成在缓冲层（2100）上的高迁移率III-V族化合物半导体层（2000）。

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