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41. 发明申请

US20120326217A1 SEMICONDUCTOR DEVICE INCLUDING MULTIPLE METAL SEMICONDUCTOR ALLOY REGION AND A GATE STRUCTURE COVERED BY A CONTINUOUS ENCAPSULATING LAYER 有权
标题翻译：包括多个金属半导体合金区域的半导体器件和由连续封装层覆盖的栅极结构
公开(公告)号：US20120326217A1
公开(公告)日：2012-12-27
申请号：US13604143
申请日：2012-09-05
申请人： Sivananda K. Kanakasabapathy , Hemanth Jagannathan , Soon-Cheon Seo
发明人： Sivananda K. Kanakasabapathy , Hemanth Jagannathan , Soon-Cheon Seo
IPC分类号： H01L29/78
CPC分类号： H01L29/78606 , H01L21/823835 , H01L29/4908 , H01L29/4966 , H01L29/66545 , H01L29/66772
摘要： A method of forming a semiconductor device is provided that in some embodiments encapsulates a gate silicide in a continuous encapsulating material. By encapsulating the gate silicide in the encapsulating material, the present disclosure substantially eliminates shorting between the gate structure and the interconnects to the source and drain regions of the semiconductor device.
摘要翻译：提供了一种形成半导体器件的方法，其在一些实施例中将栅极硅化物封装在连续封装材料中。通过将栅极硅化物封装在封装材料中，本公开基本上消除了栅极结构与半导体器件的源极和漏极区域的互连之间的短路。

42. 发明申请

US20120181613A1 Methods for Forming Field Effect Transistor Devices With Protective Spacers 审中-公开
标题翻译：用保护隔离层形成场效应晶体管器件的方法
公开(公告)号：US20120181613A1
公开(公告)日：2012-07-19
申请号：US13009271
申请日：2011-01-19
申请人： Veeraraghavan S. Basker , Toshiharu Furukawa , Steven J. Holmes , Sivananda K. Kanakasabapathy
发明人： Veeraraghavan S. Basker , Toshiharu Furukawa , Steven J. Holmes , Sivananda K. Kanakasabapathy
IPC分类号： H01L27/088 , H01L21/8234 , H01L21/8238
CPC分类号： H01L29/66477 , H01L21/823418 , H01L21/823468 , H01L29/78
摘要： A method for forming a field effect transistor device includes forming a first gate stack and a second gate stack on a substrate, depositing a first photoresist material over the second gate stack and a portion of the substrate, implanting ions in exposed regions of the substrate to define a first source region and a first drain region adjacent to the first gate stack, depositing a first protective layer over the first source region, the first gate stack, the first drain region, and the first photoresist material, removing portions of the first protective layer to expose the first photoresist material and to define a first spacer disposed on a portion of the first source region and a portion of the first drain region, removing the first photoresist material, and removing the first spacer.
摘要翻译：一种用于形成场效应晶体管器件的方法包括在衬底上形成第一栅极堆叠和第二栅极叠层，在第二栅极堆叠上沉积第一光致抗蚀剂材料和衬底的一部分，将衬底的暴露区域中的离子注入到限定与第一栅极堆叠相邻的第一源极区域和第一漏极区域，在第一源极区域，第一栅极堆叠层，第一漏极区域和第一光致抗蚀剂材料上沉积第一保护层，去除第一保护层以露出第一光致抗蚀剂材料并且限定设置在第一源极区域和第一漏极区域的一部分上的第一间隔物，去除第一光致抗蚀剂材料，以及移除第一间隔物。

43. 发明申请

US20120068346A1 STRUCTURE FOR NANO-SCALE METALLIZATION AND METHOD FOR FABRICATING SAME 有权
标题翻译：用于纳米尺度金属化的结构及其制造方法
公开(公告)号：US20120068346A1
公开(公告)日：2012-03-22
申请号：US12885665
申请日：2010-09-20
申请人： SHOM PONOTH , David V. Horak , Elbert E. Huang , Sivananda K. Kanakasabapathy , Charles W. Koburger, III , Chih-Chao Yang
发明人： SHOM PONOTH , David V. Horak , Elbert E. Huang , Sivananda K. Kanakasabapathy , Charles W. Koburger, III , Chih-Chao Yang
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L23/53266 , H01L21/32139 , H01L21/76885 , H01L21/76897 , H01L23/5283 , H01L2924/0002 , H01L2924/00
摘要： A method for forming structure aligned with features underlying an opaque layer is provided for an interconnect structure, such as an integrated circuit. In one embodiment, the method includes forming an opaque layer over a first layer, the first layer having a surface topography that maps to at least one feature therein, wherein the opaque layer is formed such that the surface topography is visible over the opaque layer. A second feature is positioned and formed in the opaque layer by reference to such surface topography.
摘要翻译：为诸如集成电路的互连结构提供了用于形成与不透明层下面的特征对准的结构的方法。在一个实施例中，该方法包括在第一层上形成不透明层，第一层具有映射到其中的至少一个特征的表面形貌，其中不透明层被形成为使得表面形貌在不透明层上可见。通过参考这种表面形貌，第二特征被定位并形成在不透明层中。

44. 发明申请

US20110111596A1 Sidewall Image Transfer Using the Lithographic Stack as the Mandrel 失效
标题翻译：侧壁图像传输使用光刻堆栈作为心轴
公开(公告)号：US20110111596A1
公开(公告)日：2011-05-12
申请号：US12613682
申请日：2009-11-06
申请人： Sivananda K. Kanakasabapathy
发明人： Sivananda K. Kanakasabapathy
IPC分类号： H01L21/30
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L29/66795
摘要： In one non-limiting exemplary embodiment, a method includes: providing a structure having at least one lithographic layer on a substrate, where the at least one lithographic layer includes a planarization layer (PL); forming a sacrificial mandrel by patterning at least a portion of the at least one lithographic layer using a photolithographic process, where the sacrificial mandrel includes at least a portion of the PL; and producing at least one microstructure by using the sacrificial mandrel in a sidewall image transfer process.
摘要翻译：在一个非限制性示例性实施例中，一种方法包括：提供在衬底上具有至少一个光刻层的结构，其中所述至少一个光刻层包括平坦化层（PL）; 通过使用光刻工艺图案化所述至少一个光刻层的至少一部分来形成牺牲心轴，其中所述牺牲心轴包括所述PL的至少一部分; 以及通过在侧壁图像转印过程中使用牺牲心轴来生产至少一个微结构。

45. 发明授权

US07642147B1 Methods for removing sidewall spacers 失效
标题翻译：去除侧壁间隔物的方法
公开(公告)号：US07642147B1
公开(公告)日：2010-01-05
申请号：US12242977
申请日：2008-10-01
申请人： Sivananda K. Kanakasabapathy
发明人： Sivananda K. Kanakasabapathy
IPC分类号： H01L21/8238
CPC分类号： H01L29/665 , H01L21/28097 , H01L21/823807 , H01L21/823864 , H01L21/84 , H01L27/1203 , H01L29/4908 , H01L29/4975 , H01L29/6653 , H01L29/6659 , H01L29/7843
摘要： A method for removing sidewall spacers. The method includes: (a) forming a gate stack on a substrate; after (a), (b) forming dielectric spacers on sidewalls of the gate stack; after (b), (c) forming a dielectric sacrificial layer over the substrate and on the gate stack where the substrate and the gate stack are not covered by the spacers; and after (c), (d) removing the sacrificial layer and the spacers in a etch process by etching the sacrificial layer until the spacers are exposed and thereafter simultaneously etching the sacrificial layer and the spacers until the sacrificial layer and the spacers are removed. Methods for spacer removal from PFETs when a stress layer is formed over the NFETs are also disclosed.
摘要翻译：一种去除侧壁间隔物的方法。该方法包括：（a）在基板上形成栅叠层; （a）之后，（b）在栅叠层的侧壁上形成电介质间隔物; （b）之后，（c）在基板和栅叠层上形成绝缘牺牲层，其中衬底和栅极堆叠不被间隔物覆盖; 在（c）之后，（d）通过蚀刻牺牲层去除牺牲层和间隔物，直到间隔物被暴露，然后同时蚀刻牺牲层和间隔物，直到除去牺牲层和间隔物。还公开了当在NFET上形成应力层时从PFET去除间隔物的方法。

46. 发明授权

US07507633B2 Method and structure for improved alignment in MRAM integration 有权
标题翻译：改善MRAM集成对齐的方法和结构
公开(公告)号：US07507633B2
公开(公告)日：2009-03-24
申请号：US11369516
申请日：2006-03-07
申请人： Sivananda K. Kanakasabapathy , David W. Abraham
发明人： Sivananda K. Kanakasabapathy , David W. Abraham
IPC分类号： H01L21/76
CPC分类号： H01L23/544 , H01L27/222 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： A method for implementing alignment of a semiconductor device structure includes forming first and second sets of alignment marks within a lower level of the structure, the second set of alignment marks adjacent the first set of alignment marks. An opaque layer is formed over the lower level, including the first and second sets of alignment marks. A portion of the opaque layer corresponding to the location of said first set of alignment marks is opened so as to render the first set optically visible while the second set of alignment marks initially remains covered by the opaque layer. The opaque layer is patterned using the optically visible first set of alignment marks, wherein the second set of alignment marks remain available for subsequent alignment operations in the event the first set becomes damaged during patterning of the opaque layer.
摘要翻译：用于实现半导体器件结构的对准的方法包括在该结构的较低级别内形成第一组和第二组对准标记，第二组对准标记与第一组对准标记相邻。在较低层上形成不透明层，包括第一组和第二组对准标记。对应于所述第一组对准标记的位置的不透明层的一部分被打开，以使第一组光学可见，而第二组对准标记最初保持被不透明层覆盖。使用光学可见的第一组对准标记图案化不透明层，其中在第一组在不透明层的图案化期间第一组变得损坏的情况下，第二组对准标记保持可用于随后的对准操作。

47. 发明申请

US20080185101A1 Hard Mask Structure for Patterning of Materials 有权
标题翻译：材料图案的硬掩模结构
公开(公告)号：US20080185101A1
公开(公告)日：2008-08-07
申请号：US12099441
申请日：2008-04-08
申请人： Michael C. Gaidis , Sivananda K. Kanakasabapathy , Eugene J. O'Sullivan
发明人： Michael C. Gaidis , Sivananda K. Kanakasabapathy , Eugene J. O'Sullivan
IPC分类号： H01L21/306
CPC分类号： H01L43/12 , H01L21/0332 , H01L21/0337 , H01L27/11507 , H01L28/65
摘要： Techniques for magnetic device fabrication are provided. In one aspect, a method of patterning at least one, e.g., nonvolatile, material comprises the following steps. A hard mask structure is formed on at least one surface of the material to be patterned. The hard mask structure is configured to have a base, proximate to the material, and a top opposite the base. The base has one or more lateral dimensions that are greater than one or more lateral dimensions of the top of the hard mask structure, such that at least one portion of the base extends out laterally a substantial distance beyond the top. The top of the hard mask structure is at a greater vertical distance from the material being etched than the base. The material is etched.
摘要翻译：提供了磁性器件制造技术。一方面，图案化至少一种，例如非挥发性材料的方法包括以下步骤。在待图案化材料的至少一个表面上形成硬掩模结构。硬掩模结构被配置为具有靠近材料的基部和与基部相对的顶部。基座具有大于硬掩模结构的顶部的一个或多个横向尺寸的一个或多个横向尺寸，使得基部的至少一部分横向延伸超过顶部的实质距离。硬掩模结构的顶部距离被蚀刻的材料比基底更大的垂直距离。材料被蚀刻。

48. 发明授权

US06933204B2 Method for improved alignment of magnetic tunnel junction elements 有权
标题翻译：改善磁性隧道结元件对准的方法
公开(公告)号：US06933204B2
公开(公告)日：2005-08-23
申请号：US10605604
申请日：2003-10-13
申请人： Chandrasekhar Sarma , Sivananda K. Kanakasabapathy , Ihar Kasko , Greg Costrini , John P. Hummel , Michael C. Gaidis
发明人： Chandrasekhar Sarma , Sivananda K. Kanakasabapathy , Ihar Kasko , Greg Costrini , John P. Hummel , Michael C. Gaidis
IPC分类号： G03F9/00 , H01L21/76 , H01L23/544 , H01L27/22
CPC分类号： H01L27/222 , G03F9/7076 , G03F9/708 , G03F9/7084 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method for aligning an opaque, active device in a semiconductor structure includes forming an opaque layer over an optically transparent layer formed on a lower metallization level, the lower metallization level including one or more alignment marks formed therein. A portion of the opaque layer is patterned and opened corresponding to the location of the one or more alignment marks in the lower metallization level so as to render the one or more alignment marks optically visible. The opaque layer is then patterned with respect to the lower metallization level, using the optically visible one or more alignment marks.
摘要翻译：用于对准半导体结构中的不透明有源器件的方法包括在形成在下金属化层上的光学透明层上形成不透明层，所述下金属化层包括其中形成的一个或多个对准标记。对应于下部金属化水平中的一个或多个对准标记的位置，对不透明层的一部分进行图案化和打开，以便使一个或多个对准标记光学可见。然后使用光学可见的一个或多个对准标记，相对于较低的金属化水平对不透明层进行图案化。

49. 发明授权

US08901670B2 Semiconductor device including multiple metal semiconductor alloy region and a gate structure covered by a continuous encapsulating layer 有权
标题翻译：半导体器件包括多个金属半导体合金区域和由连续封装层覆盖的栅极结构
公开(公告)号：US08901670B2
公开(公告)日：2014-12-02
申请号：US13604143
申请日：2012-09-05
申请人： Sivananda K. Kanakasabapathy , Hemanth Jagannathan , Soon-Cheon Seo
发明人： Sivananda K. Kanakasabapathy , Hemanth Jagannathan , Soon-Cheon Seo
IPC分类号： H01L21/02 , H01L29/786 , H01L29/49 , H01L21/8238 , H01L29/66
CPC分类号： H01L29/78606 , H01L21/823835 , H01L29/4908 , H01L29/4966 , H01L29/66545 , H01L29/66772
摘要： A method of forming a semiconductor device is provided that in some embodiments encapsulates a gate silicide in a continuous encapsulating material. By encapsulating the gate silicide in the encapsulating material, the present disclosure substantially eliminates shorting between the gate structure and the interconnects to the source and drain regions of the semiconductor device.
摘要翻译：提供了一种形成半导体器件的方法，其在一些实施例中将栅极硅化物封装在连续封装材料中。通过将栅极硅化物封装在封装材料中，本公开基本上消除了栅极结构与半导体器件的源极和漏极区域的互连之间的短路。

50. 发明授权

US08802565B2 Semiconductor plural gate lengths 有权
公开(公告)号：US08802565B2
公开(公告)日：2014-08-12
申请号：US13608211
申请日：2012-09-10
申请人： Michael J. Hartig , Sivananda K. Kanakasabapathy , Soon-Cheon Seo , Raghavasimhan Sreenivasan
发明人： Michael J. Hartig , Sivananda K. Kanakasabapathy , Soon-Cheon Seo , Raghavasimhan Sreenivasan
IPC分类号： H01L21/302
CPC分类号： H01L21/823456 , H01L29/66545
摘要： Gate structures with different gate lengths and methods of manufacture are disclosed. The method includes forming a first gate structure with a first critical dimension, using a pattern of a mask. The method further includes forming a second gate structure with a second critical dimension, different than the first critical dimension of the first gate structure, using the pattern of the mask.

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