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41. 发明授权

US07243262B2 Incremental checkpointing in a multi-threaded architecture 有权
标题翻译：多线程架构中的增量检查点
公开(公告)号：US07243262B2
公开(公告)日：2007-07-10
申请号：US10651376
申请日：2003-08-29
申请人： Shubhendu S. Mukherjee , Steven K. Reinhardt , Joel S. Emer
发明人： Shubhendu S. Mukherjee , Steven K. Reinhardt , Joel S. Emer
IPC分类号： G06F11/00
CPC分类号： G06F11/366 , G06F9/3851 , G06F9/3863 , G06F11/1494 , G06F11/1629
摘要： A processor executes corresponding instruction threads as a leading thread and a trailing thread. For a selected instruction, processor state corresponding to the execution of the instruction is saved in a history buffer. This is performed before writing a result from the selected instruction to a destination register. The result from executing the selected instruction in the leading thread is compared to the result from executing the selected instruction in the trailing thread. If the comparison indicates a fault, then restoring the processor state corresponding to a previous instruction. Data from the history buffer is used to perform the restoration.
摘要翻译：处理器执行相应的指令线程作为前导线程和尾随线程。对于所选择的指令，与指令的执行相对应的处理器状态被保存在历史缓冲器中。这是在将所选指令的结果写入目的寄存器之前进行的。在前导线程中执行所选择的指令的结果与执行拖尾线程中所选指令的结果进行比较。如果比较指示故障，则恢复与先前指令相对应的处理器状态。来自历史缓冲区的数据用于执行恢复。

42. 发明授权

US06108770A Method and apparatus for predicting memory dependence using store sets 失效
标题翻译：使用存储集来预测存储器依赖性的方法和装置
公开(公告)号：US06108770A
公开(公告)日：2000-08-22
申请号：US103984
申请日：1998-06-24
申请人： George Z. Chrysos , Joel S. Emer , Bruce E. Edwards , John H. Edmondson
发明人： George Z. Chrysos , Joel S. Emer , Bruce E. Edwards , John H. Edmondson
IPC分类号： G06F9/312 , G06F9/38
CPC分类号： G06F9/30043 , G06F9/3834 , G06F9/3838 , G06F9/3861
摘要： A method of scheduling program instructions for execution in a computer processor comprises fetching and holding instructions from an instruction memory and executing the fetched instructions out of program order. When load/store order violations are detected, the effects of the load operation and its dependent instructions are erased and they are re-executed. The load is associated with all stores on whose data the load depends. This collection of stores is called a store set. On a subsequent issuance of the load, its execution is delayed until any store in the load's store set has issued. Two loads may share a store set, and separate store sets are merged when a load from one store set is found to depend on a store from another store set. A preferred embodiment employs two tables. The first is a store set ID table (SSIT) which is indexed by part of, or a hash of, an instruction PC. Entries in the SSIT provide a store set ID which is used to index into the second table, which for each store set, contains a pointer to the last fetched, unexecuted store instruction.
摘要翻译：调度用于在计算机处理器中执行的程序指令的方法包括从指令存储器读取和保存指令，并从程序顺序执行所取出的指令。当检测到加载/存储订单违规时，擦除负载操作及其相关指令的影响，并重新执行。负载与负载所依赖的数据的所有存储相关联。这个商店集合被称为商店集。在随后的负载发放中，其执行被延迟，直到装载商店中的任何商店已经发出。两个负载可以共享存储集，并且当发现来自一个存储集的负载依赖于来自另一个存储集的存储时，分离的存储集被合并。优选实施例采用两个表。第一个是由指令PC的一部分或散列构成索引的存储集ID表（SSIT）。 SSIT中的条目提供存储集ID，该存储集ID用于索引到第二表，对于每个存储集，对于每个存储集，ID包含指向最后获取的未执行存储指令的指针。

43. 发明授权

US5428807A Method and apparatus for propagating exception conditions of a computer system 失效
标题翻译：传播计算机系统异常情况的方法和装置
公开(公告)号：US5428807A
公开(公告)日：1995-06-27
申请号：US79498
申请日：1993-06-17
申请人： Francis X. McKeen , Michael C. Adler , Joel S. Emer , Robert P. Nix , David J. Sager , P. Geoffrey Lowny
发明人： Francis X. McKeen , Michael C. Adler , Joel S. Emer , Robert P. Nix , David J. Sager , P. Geoffrey Lowny
IPC分类号： G06F9/38 , G06F9/00
CPC分类号： G06F9/3865 , G06F9/3834 , G06F9/3842 , G06F9/3863
摘要： There is provided a mechanism for propagating exception conditions in a computer system when instructions are subject to exception conditions. The apparatus includes a set of data registers for storing data manipulated by the instructions of the computer system, and a set of state registers for storing speculative states of data manipulated by the instructions, there being one state register associated with each data register. Furthermore, the apparatus includes a logic circuit, coupled to the set of state registers, for propagating the states from a source one of the state registers to a destination one of the state registers, if data stored in an associated source one of the data registers are used as a source for an associated destination one of data registers, and if data stored in the source data register were manipulated by a particular instruction subject to an exception condition.
摘要翻译：当指令受到异常条件的限制时，提供了一种在计算机系统中传播异常情况的机制。该装置包括一组数据寄存器，用于存储由计算机系统的指令操纵的数据，以及一组状态寄存器，用于存储由指令操纵的数据的推测状态，存在与每个数据寄存器相关联的一个状态寄存器。此外，该装置包括耦合到一组状态寄存器的逻辑电路，用于将状态从状态寄存器中的一个状态寄存器传播到状态寄存器的目的地寄存器，如果数据存储在相关源中的一个数据寄存器被用作相关联的目的地数据寄存器的源，并且如果存储在源数据寄存器中的数据被受异常条件的特定指令操纵。

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