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41. 发明授权

US08692322B2 Flexible Crss adjustment in a SGT MOSFET to smooth waveforms and to avoid EMI in DC-DC application 有权
标题翻译： SGT MOSFET中的灵活Crss调整可平滑波形，并避免DC-DC应用中的EMI
公开(公告)号：US08692322B2
公开(公告)日：2014-04-08
申请号：US13539330
申请日：2012-08-26
申请人： Ji Pan , Daniel Ng , Anup Bhalla , Xiaobin Wang
发明人： Ji Pan , Daniel Ng , Anup Bhalla , Xiaobin Wang
IPC分类号： H01L27/088
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/407 , H01L29/41741 , H01L29/41766 , H01L29/42372 , H01L29/4238 , H01L29/456 , H01L29/4933 , H01L29/66727 , H01L29/66734 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor power device comprises a plurality of power transistor cells each having a trenched gate disposed in a gate trench wherein the trenched gate comprising a shielding bottom electrode disposed in a bottom portion of the gate trench electrically insulated from a top gate electrode disposed in a top portion of the gate trench by an inter-electrode insulation layer. At least one of the transistor cells includes the shielding bottom electrode functioning as a source-connecting shielding bottom electrode electrically connected to a source electrode of the semiconductor power device and at least one of the transistor cells having the shielding bottom electrode functioning as a gate-connecting shielding bottom electrode electrically connected to a gate metal of the semiconductor power device.
摘要翻译：半导体功率器件包括多个功率晶体管单元，每个功率晶体管单元各自具有设置在栅极沟槽中的沟槽栅极，其中沟槽栅极包括设置在栅极沟槽的底部部分中的屏蔽底部电极，该顶部电极与设置在顶部的顶部栅电极电绝缘栅极沟槽的部分通过电极间绝缘层。晶体管单元中的至少一个包括用作与半导体功率器件的源电极电连接的源极连接屏蔽底部电极的屏蔽底部电极，以及具有用作栅极连接的屏蔽底部电极的至少一个晶体管单元，连接屏蔽底电极，电连接到半导体功率器件的栅极金属。

42. 发明申请

US20130015550A1 JUNCTION BARRIER SCHOTTKY DIODE WITH ENFORCED UPPER CONTACT STRUCTURE AND METHOD FOR ROBUST PACKAGING 有权
标题翻译：具有强化接触结构的结构障碍物肖特基二极管和用于稳定包装的方法
公开(公告)号：US20130015550A1
公开(公告)日：2013-01-17
申请号：US13184488
申请日：2011-07-15
申请人： Anup Bhalla , Ji Pan , Daniel Ng
发明人： Anup Bhalla , Ji Pan , Daniel Ng
IPC分类号： H01L29/872 , H01L21/283
CPC分类号： H01L29/872 , H01L24/05 , H01L29/0619 , H01L29/417 , H01L2924/01029 , H01L2924/12032 , H01L2924/00
摘要： A semiconductor junction barrier Schottky (JBS-SKY) diode with enforced upper contact structure (EUCS) is disclosed. Referencing an X-Y-Z coordinate, the JBS-SKY diode has semiconductor substrate (SCST) parallel to X-Y plane. Active device zone (ACDZ) atop SCST and having a JBS-SKY diode with Z-direction current flow. Peripheral guarding zone (PRGZ) atop SCST and surrounding the ACDZ. The ACDZ has active lower semiconductor structure (ALSS) and enforced active upper contact structure (EUCS) atop ALSS. The EUC has top contact metal (TPCM) extending downwards and in electrical conduction with bottom of EUCS; and embedded bottom supporting structure (EBSS) inside TPCM and made of a hard material, the EBSS extending downwards till bottom of the EUCS. Upon encountering bonding force onto TPCM during packaging of the JBS-SKY diode, the EBSS enforces the EUCS against an otherwise potential micro cracking of the TPCM degrading the leakage current of the JBS-SKY diode.
摘要翻译：公开了一种具有强制上接触结构（EUCS）的半导体结屏障肖特基（JBS-SKY）二极管。参考X-Y-Z坐标，JBS-SKY二极管具有与X-Y平面平行的半导体衬底（SCST）。有源器件区（ACDZ）位于SCST上方，并具有Z方向电流流动的JBS-SKY二极管。外围防护区（PRGZ）在SCST顶部并围绕ACDZ。 ACDZ在ALSS顶部具有活性较低的半导体结构（ALSS）和强制性的上接触结构（EUCS）。 EUC具有向下延伸并与EUCS底部导电的顶部接触金属（TPCM）; 并在TPCM内部嵌入底部支撑结构（EBSS），由硬质材料制成，EBSS向下延伸至EUCS底部。在JBS-SKY二极管封装期间遇到TPCM上的结合力时，EBSS强制EUCS抵抗TPCM的另外潜在的微裂纹，降低JBS-SKY二极管的漏电流。

43. 发明授权

US08163618B2 Power MOSFET device structure for high frequency applications 有权
标题翻译：功率MOSFET器件结构用于高频应用
公开(公告)号：US08163618B2
公开(公告)日：2012-04-24
申请号：US12658450
申请日：2010-02-09
申请人： Anup Bhalla , Daniel Ng , Tiesheng Li , Sik K. Lui
发明人： Anup Bhalla , Daniel Ng , Tiesheng Li , Sik K. Lui
IPC分类号： H01L21/336
CPC分类号： H01L29/66712 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/41775 , H01L29/42368 , H01L29/42372 , H01L29/42376 , H01L29/66719 , H01L29/66727 , H01L29/7802 , H01L29/7811 , H01L29/7827
摘要： This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current. The switching device further includes a source electrode interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region. The semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than the drain region. The insulated gate electrode further includes an insulation layer for insulating the gate electrode from the source electrode wherein the insulation layer having a thickness depending on a Vgsmax rating of the vertical power device.
摘要翻译：本发明公开了一种支撑在半导体上的新开关装置，其包括设置在第一表面上的漏极和设置在与第一表面相对的所述半导体的第二表面附近的源极区域。开关装置还包括设置在第二表面顶部的用于控制源极到漏极电流的绝缘栅电极。开关装置还包括插入到绝缘栅电极中的源电极，用于基本上防止栅电极和绝缘栅电极下方的外延区之间的电场的耦合。源电极进一步覆盖并延伸在绝缘栅上，以覆盖半导体的第二表面上的区域以接触源区。半导体衬底还包括设置在漏极区以上且具有与漏极区不同的掺杂浓度的外延层。绝缘栅电极还包括用于使栅电极与源电极绝缘的绝缘层，其中绝缘层的厚度取决于垂直功率器件的Vgsmax等级。

44. 发明申请

US20110198605A1 Termination Structure with Multiple Embedded Potential Spreading Capacitive Structures for Trench MOSFET and Method 有权
标题翻译：具有多个嵌入式电位扩展结构的端接结构，用于沟槽MOSFET和方法
公开(公告)号：US20110198605A1
公开(公告)日：2011-08-18
申请号：US12704528
申请日：2010-02-12
申请人： Xiaobin Wang , Anup Bhalla , Hamza Yilmaz , Daniel Ng
发明人： Xiaobin Wang , Anup Bhalla , Hamza Yilmaz , Daniel Ng
IPC分类号： H01L29/94 , H01L21/02
CPC分类号： H01L29/407 , H01L21/76205 , H01L29/04 , H01L29/0619 , H01L29/0638 , H01L29/0649 , H01L29/0696 , H01L29/402 , H01L29/41766 , H01L29/42368 , H01L29/66727 , H01L29/66734 , H01L29/7803 , H01L29/7811 , H01L29/7813 , H01L2924/0002 , H01L2924/00
摘要： A termination structure with multiple embedded potential spreading capacitive structures (TSMEC) and method are disclosed for terminating an adjacent trench MOSFET atop a bulk semiconductor layer (BSL) with bottom drain electrode. The BSL has a proximal bulk semiconductor wall (PBSW) supporting drain-source voltage (DSV) and separating TSMEC from trench MOSFET. The TSMEC has oxide-filled large deep trench (OFLDT) bounded by PBSW and a distal bulk semiconductor wall (DBSW). The OFLDT includes a large deep oxide trench into the BSL and embedded capacitive structures (EBCS) located inside the large deep oxide trench and between PBSW and DBSW for spatially spreading the DSV across them. In one embodiment, the EBCS contains interleaved conductive embedded polycrystalline semiconductor regions (EPSR) and oxide columns (OXC) of the OFLDT, a proximal EPSR next to PBSW is connected to an active upper source region and a distal EPSR next to DBSW is connected to the DBSW.
摘要翻译：公开了具有多个嵌入式电位扩展电容结构（TSMEC）和方法的端接结构，用于在具有底部漏电极的体半导体层（BSL）的顶部端接邻近的沟槽MOSFET。 BSL具有支持漏极 - 源极电压（DSV）的近端体半导体壁（PBSW），并将TSMEC与沟槽MOSFET分离。 TSMEC具有由PBSW和远端体半导体壁（DBSW）界定的氧化物填充的大深沟槽（OFLDT）。 OFLDT包括位于大深度氧化物沟槽内部以及PBSW和DBSW之间的BSL中的大型深层氧化物沟槽和嵌入式电容结构（EBCS），用于在其间空间扩展DSV。在一个实施例中，EBCS包含OFLDT的交错导电嵌入式多晶半导体区域（EPSR）和氧化物柱（OXC），与PBSW相邻的近端EPSR连接到活动上部源区域，并且与DBSW相邻的远端EPSR被连接到星展集团

45. 发明授权

US07943989B2 Nano-tube MOSFET technology and devices 有权
公开(公告)号：US07943989B2
公开(公告)日：2011-05-17
申请号：US12319164
申请日：2008-12-31
申请人： Hamza Yilmaz , Daniel Ng , Lingpeng Guan , Anup Bhalla , Wilson Ma , Moses Ho , John Chen
发明人： Hamza Yilmaz , Daniel Ng , Lingpeng Guan , Anup Bhalla , Wilson Ma , Moses Ho , John Chen
IPC分类号： H01L29/66
CPC分类号： H01L29/7827 , H01L29/0619 , H01L29/0634 , H01L29/0638 , H01L29/0649 , H01L29/0653 , H01L29/0696 , H01L29/0878 , H01L29/404 , H01L29/66136 , H01L29/66348 , H01L29/66666 , H01L29/66734 , H01L29/7322 , H01L29/7395 , H01L29/7397 , H01L29/7802 , H01L29/7811 , H01L29/7813 , H01L29/8083 , H01L29/861 , H01L29/872
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.

46. 发明申请

US20130221430A1 NANO-TUBE MOSFET TECHNOLOGY AND DEVICES 有权
标题翻译：纳米管MOSFET技术和器件
公开(公告)号：US20130221430A1
公开(公告)日：2013-08-29
申请号：US13594837
申请日：2012-08-26
申请人： Hamza Yilmaz , Daniel Ng , Lingpeng Guan , Anup Bhalla , Wilson Ma , Moses Ho , John Chen
发明人： Hamza Yilmaz , Daniel Ng , Lingpeng Guan , Anup Bhalla , Wilson Ma , Moses Ho , John Chen
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7827 , H01L29/0619 , H01L29/0634 , H01L29/0638 , H01L29/0649 , H01L29/0653 , H01L29/0696 , H01L29/0878 , H01L29/404 , H01L29/66136 , H01L29/66348 , H01L29/66666 , H01L29/66734 , H01L29/7322 , H01L29/7395 , H01L29/7397 , H01L29/7802 , H01L29/7811 , H01L29/7813 , H01L29/8083 , H01L29/861 , H01L29/872
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.
摘要翻译：本发明公开了一种设置在半导体衬底中的半导体功率器件，半导体衬底具有多个沟槽。每个沟槽填充有多个交替导电类型的外延层，其构成纳米管，其功能是作为沿着侧壁方向延伸的层堆叠的导电通道，“间隙填充”层填充基本上位于其上的纳米管之间的合并间隙每个沟渠的中心。 “间隙填料”层可以非常轻掺杂硅或生长和沉积的介电层。在一个示例性实施例中，多个沟槽被柱柱分隔开，柱柱各自具有沟槽宽度的大约一半到三分之一的宽度。

47. 发明申请

US20130093001A1 POWER MOSFET DEVICE STRUCTURE FOR HIGH FREQUENCY APPLICATIONS 有权
标题翻译：功率MOSFET器件结构高频应用
公开(公告)号：US20130093001A1
公开(公告)日：2013-04-18
申请号：US13436192
申请日：2012-03-30
申请人： Anup Bhalla , Daniel Ng , Tiesheng Li , Sik K. Lui
发明人： Anup Bhalla , Daniel Ng , Tiesheng Li , Sik K. Lui
IPC分类号： H01L29/78
CPC分类号： H01L29/66712 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/41775 , H01L29/42368 , H01L29/42372 , H01L29/42376 , H01L29/66719 , H01L29/66727 , H01L29/7802 , H01L29/7811 , H01L29/7827
摘要： This invention discloses a new switching device that includes a drain disposed on a first surface and a source region disposed near a second surface of a semiconductor opposite the first surface. An insulated gate electrode is disposed on top of the second surface for controlling a source to drain current and a source electrode is interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region, An epitaxial layer is disposed above and having a different dopant concentration than the drain region. The gate electrode is insulated from the source electrode by an insulation layer having a thickness depending on a Vgsmax rating of the vertical power device.
摘要翻译：本发明公开了一种新的开关装置，其包括设置在第一表面上的漏极和设置在与第一表面相对的半导体的第二表面附近的源极区域。绝缘栅电极设置在第二表面的顶部，用于控制源极到漏极电流，并且源电极插入到绝缘栅电极中，用于基本上防止栅极电极和绝缘栅极之间的外延区域之间的电场的耦合栅电极。源极电极进一步覆盖并延伸在绝缘栅上，用于覆盖半导体的第二表面上的区域以接触源极区。外延层设置在漏极区之上并且具有不同掺杂剂浓度。栅极通过具有取决于垂直功率器件的Vgsmax额定值的厚度的绝缘层与源电极绝缘。

48. 发明申请

US20120126317A1 ACCUFET WITH INTEGRATED CLAMPING CIRCUIT 审中-公开
标题翻译：具有集成钳位电路的ACCUFET
公开(公告)号：US20120126317A1
公开(公告)日：2012-05-24
申请号：US12949218
申请日：2010-11-18
申请人： Daniel Ng , Anup Bhalla , Xiaobin Wang
发明人： Daniel Ng , Anup Bhalla , Xiaobin Wang
IPC分类号： H01L27/06 , H01L21/8234
CPC分类号： H01L27/0727 , H01L27/0629 , H01L29/872
摘要： The present invention features a field effect transistor that includes a semiconductor substrate having gate, source and drain regions; and a p-n junction formed on the semiconductor substrate and in electrical communication with the gate, drain and source regions to establish a desired breakdown voltage. In one embodiment, gate region further includes a plurality of spaced-apart trench gates with the p-n junction being defined by an interface between an epitaxial layer in which the trench gates are formed and the interface with a metallization layer. The breakdown voltage provided is defined, in part by the number of p-n junctions formed. In another embodiment, the p-n junctions are formed by generating a plurality of spaced-apart p-type regions in areas of the epitaxial layer located adjacent to the trench gates.
摘要翻译：本发明的特征在于一种场效应晶体管，其包括具有栅极，源极和漏极区域的半导体衬底; 以及形成在半导体衬底上并与栅极，漏极和源极区域电连通以建立期望的击穿电压的p-n结。在一个实施例中，栅极区域还包括多个间隔开的沟槽栅极，其中p-n结由其中形成沟槽栅极的外延层与与金属化层的界面之间的界面限定。提供的击穿电压部分地由形成的p-n结的数量定义。在另一个实施例中，通过在邻近沟槽栅极定位的外延层的区域中产生多个间隔开的p型区域来形成p-n结。

49. 发明申请

US20090219044A1 Calibration technique for measuring gate resistance of power MOS gate device at wafer level 有权
标题翻译：用于在晶圆级测量功率MOS栅极器件的栅极电阻的校准技术
公开(公告)号：US20090219044A1
公开(公告)日：2009-09-03
申请号：US12454004
申请日：2009-05-11
申请人： Anup Bhalla , Sik K. Lui , Daniel Ng
发明人： Anup Bhalla , Sik K. Lui , Daniel Ng
IPC分类号： G01R31/26 , G01R31/02
CPC分类号： H04L63/102 , G01R31/2625 , G01R31/2884 , G01R35/005 , H01L22/14 , H01L2924/0002 , H04L63/08 , H01L2924/00
摘要： This invention discloses a method for calibrating a gate resistance measurement of a semiconductor power device that includes a step of forming a RC network on a test area on a semiconductor wafer adjacent to a plurality of semiconductor power chips and measuring a resistance and a capacitance of the RC network to prepare for carrying out a wafer-level measurement calibration of the semiconductor power device. The method further includes a step of connecting a probe card to a set of contact pads on the semiconductor wafer for carrying out the wafer-level measurement calibration followed by performing a gate resistance Rg measurement for the semiconductor power chips.
摘要翻译：本发明公开了一种用于校准半导体功率器件的栅极电阻测量的方法，包括在与多个半导体功率芯片相邻的半导体晶片上的测试区域上形成RC网络的步骤，并测量电阻和电容 RC网络，准备进行半导体功率器件的晶圆级测量校准。该方法还包括将探针卡连接到半导体晶片上的一组接触焊盘，以执行晶片级测量校准，然后对半导体功率芯片执行栅极电阻Rg测量。

50. 发明授权

US07436022B2 Enhancing Schottky breakdown voltage (BV) without affecting an integrated MOSFET-Schottky device layout 有权
标题翻译：增强肖特基击穿电压（BV），而不影响集成MOSFET肖特基器件布局
公开(公告)号：US07436022B2
公开(公告)日：2008-10-14
申请号：US11413249
申请日：2006-04-29
申请人： Anup Bhalla , Daniel Ng , Sik K Lui
发明人： Anup Bhalla , Daniel Ng , Sik K Lui
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7813 , H01L29/0615 , H01L29/0619 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7811 , H01L29/872
摘要： This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells and a junction barrier Schottky (JBS) area. The semiconductor power device includes the JBS area that further includes a plurality of Schottky diodes each having a PN junction disposed on an epitaxial layer near a top surface of a semiconductor substrate wherein the PN junction further includes a counter dopant region disposed in the epitaxial layer for reducing a sudden reversal of dopant profile near the PN junction for preventing an early breakdown in the PN junction.
摘要翻译：本发明公开了一种半导体功率器件，其包括具有多个功率晶体管单元和接合势垒肖特基（JBS）区域的有源单元区域。半导体功率器件包括JBS区域，其还包括多个肖特基二极管，每个肖特基二极管各自具有设置在半导体衬底的顶表面附近的外延层上的PN结，其中PN结还包括设置在外延层中的反掺杂剂区域减少PN结附近的掺杂剂分布的突然反转，以防止PN结中的早期击穿。

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