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    • 41. 发明申请
    • IMAGE MANAGEMENT APPARATUS, IMAGE MANAGEMENT METHOD, AND RECORDING MEDIUM RECORDING PROGRAM
    • 图像管理装置,图像管理方法和记录媒体记录程序
    • US20090040340A1
    • 2009-02-12
    • US12187288
    • 2008-08-06
    • Yuichi NakaseYousuke TakagiYasuyuki OgawaKoji Hatanaka
    • Yuichi NakaseYousuke TakagiYasuyuki OgawaKoji Hatanaka
    • H04N5/76G06F7/06G06F17/30
    • H04N5/772G06F16/54G06F16/58H04N5/765H04N9/7921H04N9/8205
    • An image management apparatus includes: a narrowing-down reproduction unit for reproducing an image having particular attribute information; an attribute modification unit for modifying attribute information of the image under narrowing-down reproduction; an attribute modified image information storing unit configured to store information indicating the image which no longer contains the particular attribute information because of the modification performed on the attribute information by the attribute modification unit; and a control unit for performing control so as to regard the image indicated with the information stored in the attribute modified image information storing unit as a narrowing-down reproduction target image during the same narrowing-down reproduction as that at the time of modifying the attributes by said attribute modification unit, thereby enabling browsing of images including an image of which the attributes have been modified in a narrowing-down state, using a smaller storage area.
    • 图像管理装置包括:缩小再现单元,用于再现具有特定属性信息的图像; 属性修改单元,用于在缩小再现的范围内修改图像的属性信息; 属性修改图像信息存储单元,被配置为存储指示不再包含特定属性信息的图像的信息,因为由属性修改单元对属性信息执行的修改; 以及控制单元,用于执行控制,以便在与修改属性时相同的缩小缩小再现期间将存储在属性修改图像信息存储单元中的信息所指示的图像视为缩小再现目标图像 通过所述属性修改单元,从而能够使用较小的存储区域浏览包括属性已经在缩小状态中被修改的图像的图像。
    • 44. 发明授权
    • Bi-directional shift register and display device using same
    • 双向移位寄存器和使用其的显示装置
    • US07151523B2
    • 2006-12-19
    • US10409056
    • 2003-04-09
    • Hiroyuki OhkawaYasuyuki OgawaTamotsu SakaiKazuhiro Maeda
    • Hiroyuki OhkawaYasuyuki OgawaTamotsu SakaiKazuhiro Maeda
    • G09G3/36
    • G11C19/00G09G3/3688G09G2310/0283
    • A driving circuit of the present invention includes a signal line switching circuit section that connects each signal line with two adjacent ones of output stages of a shift register circuit, one of the two adjacent ones of output stages following the other, switches over so that the signal lines are, in the switching-over manner and in concert, driven either by the following output stages or by the followed output stages. Thus, it is possible to provide a driving circuit that can be freely placed in any manner, is suitable for many purposes, and is capable of switching shifting directions without needing inversion of a clock signal and without causing shift of pixels, and switching the shifting directions with a simple arrangement even if there are an even number of signal lines for driving effective pixel columns.
    • 本发明的驱动电路包括信号线切换电路部分,其将每个信号线与移位寄存器电路的两个输出级的两个相邻的输出级相连接,其中两个相邻的输出级中的一个依次切换,使得 信号线以切换方式和一致的方式由以下输出级或随后的输出级驱动。 因此,可以提供可以以任何方式自由放置的驱动电路,适用于许多目的,并且能够切换移位方向,而不需要时钟信号的反转而不引起像素的移位,并且切换移位 即使存在偶数个用于驱动有效像素列的信号线的方向也是简单的布置。
    • 50. 发明授权
    • Shift register and display device having the same
    • 移位寄存器和具有相同功能的显示设备
    • US09330782B2
    • 2016-05-03
    • US13805769
    • 2011-04-04
    • Kaoru YamamotoYasuyuki Ogawa
    • Kaoru YamamotoYasuyuki Ogawa
    • G11C19/18G11C19/28G09G3/36
    • G11C19/28G09G3/36G09G3/3677G09G2310/0286G11C19/184
    • A shift register 10 is configured such that m unit circuits 11 each including a shift unit 12 and three buffer units 13r, 13g, and 13b are in a multi-stage cascade connection and that 3m signals in total including three signals from each stage are outputted. The m shift units 12 perform a shift operation, and a first signal Y is outputted from each stage. When a clock signal CK is at a high level, the first signal Y rises higher than a normal high level due to bootstrapping. The buffer unit 13r controls an output signal YR to be at a high level based on the buffer control signal CR and the first signal Y. A buffer control circuit 7 controls buffer control signals CR, CG, and CB to be at a high level for a time period shorter than a half cycle of the clock signal. With this, a shift register with a reduced circuit amount and low power consumption is provided.
    • 移位寄存器10被配置为使得包括移位单元12和三个缓冲单元13r,13g和13b的m个单元电路11处于多级级联连接,并且总共包括来自每个级的三个信号的3m信号 。 m移位单元12执行移位操作,并且从每个级输出第一信号Y. 当时钟信号CK处于高电平时,由于引导,第一信号Y比正常高电平上升。 缓冲器单元13r基于缓冲器控制信号CR和第一信号Y将输出信号YR控制在高电平。缓冲器控制电路7将缓冲器控制信号CR,CG和CB控制在高电平,以便 比时钟信号的半周期短的时间段。 由此,提供了具有降低的电路量和低功耗的移位寄存器。