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41. 发明申请

US20110278732A1 Interconnect Structures for Substrate 有权
标题翻译：基板互连结构
公开(公告)号：US20110278732A1
公开(公告)日：2011-11-17
申请号：US12779734
申请日：2010-05-13
申请人： Chen-Hua Yu , Wen-Chih Chiou , Shin-Puu Jeng , Tsang-Jiuh Wu
发明人： Chen-Hua Yu , Wen-Chih Chiou , Shin-Puu Jeng , Tsang-Jiuh Wu
IPC分类号： H01L23/522 , H01L21/50
CPC分类号： H01L21/76895 , H01L21/563 , H01L21/76883 , H01L21/76898 , H01L23/147 , H01L23/481 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49894 , H01L23/5283 , H01L25/0657 , H01L25/18 , H01L2224/14181 , H01L2224/16145 , H01L2224/16225 , H01L2224/16235 , H01L2224/16238 , H01L2224/32145 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2225/06517 , H01L2225/06548 , H01L2225/06572 , H01L2225/06589 , H01L2924/01019 , H01L2924/01025 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/15311 , H01L2924/00
摘要： A device for use with integrated circuits is provided. The device includes a substrate having a through-substrate via formed therethrough. Dielectric layers are formed over at least one side of the substrate and metallization layers are formed within the dielectric layers. A first metallization layer closest to the through-substrate via is larger than one or more overlying metallization layers. In an embodiment, a top metallization layer is larger than one or more underlying metallization layers. Integrated circuit dies may be attached to the substrate on either or both sides of the substrate, and either side of the substrate may be attached to another substrate, such as a printed circuit board, a high-density interconnect, a packaging substrate, an organic substrate, a laminate substrate, or the like.
摘要翻译：提供了一种与集成电路一起使用的装置。该器件包括具有通过其形成的贯通基板通孔的基板。电介质层形成在衬底的至少一侧上，并且在电介质层内形成金属化层。最靠近贯穿衬底通孔的第一金属化层大于一个或多个上覆的金属化层。在一个实施例中，顶部金属化层大于一个或多个下面的金属化层。集成电路管芯可以在衬底的一侧或两侧附着到衬底，并且衬底的任一侧可以附接到另一衬底，例如印刷电路板，高密度互连，封装衬底，有机基板，层叠基板等。

42. 发明授权

US07994046B2 Method for forming a dielectric layer with an air gap, and a structure including the dielectric layer with the air gap 有权
标题翻译：用于形成具有气隙的电介质层的方法，以及包括具有气隙的电介质层的结构
公开(公告)号：US07994046B2
公开(公告)日：2011-08-09
申请号：US11342099
申请日：2006-01-27
申请人： Shin-Puu Jeng
发明人： Shin-Puu Jeng
IPC分类号： H01L21/4763
CPC分类号： H01L21/76814 , H01L21/7682 , H01L21/76831 , H01L21/76834 , H01L21/76843 , H01L21/76844 , Y10S438/902
摘要： A method of forming a semiconductor structure includes providing a first dielectric layer with an opening above a substrate. An exposed surface portion of the first dielectric layer in the opening is transformed. A protective dielectric layer is formed along the transformed portion of the first dielectric layer. The opening is filled with a conductive material. The transformed portion of the first dielectric layer is removed to form an air gap between the protective dielectric layer and a remaining portion of the first dielectric layer.
摘要翻译：形成半导体结构的方法包括提供在衬底上方具有开口的第一介电层。开口中的第一介电层的暴露表面部分被转变。沿着第一电介质层的变形部分形成保护电介质层。开口填充有导电材料。去除第一电介质层的变形部分以在保护电介质层和第一电介质层的剩余部分之间形成气隙。

43. 发明授权

US07952453B2 Structure design for minimizing on-chip interconnect inductance 有权
标题翻译：用于最小化片上互连电感的结构设计
公开(公告)号：US07952453B2
公开(公告)日：2011-05-31
申请号：US12759836
申请日：2010-04-14
申请人： Hsien-Wei Chen , Hsueh-Chung Chen , Shin-Puu Jeng
发明人： Hsien-Wei Chen , Hsueh-Chung Chen , Shin-Puu Jeng
IPC分类号： H01P3/08
CPC分类号： H01P3/08
摘要： A semiconductor device comprising a signal line and ground line is disclosed. The signal line comprises an opening and at least a portion of the ground line is in the opening in the signal line.
摘要翻译：公开了一种包括信号线和接地线的半导体器件。信号线包括开口，并且接地线的至少一部分在信号线中的开口中。

44. 发明授权

US07952167B2 Scribe line layout design 有权
标题翻译：划线设计
公开(公告)号：US07952167B2
公开(公告)日：2011-05-31
申请号：US11796202
申请日：2007-04-27
申请人： Hsin-Hui Lee , Mirng-Ji Lii , Shin-Puu Jeng , Shang-Yun Hou
发明人： Hsin-Hui Lee , Mirng-Ji Lii , Shin-Puu Jeng , Shang-Yun Hou
IPC分类号： H01L29/06
CPC分类号： H01L23/544 , H01L23/585 , H01L2223/5442 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A scribe line layout design to reduce the damage caused by sawing the wafer is presented. An embodiment comprises metal plates located within the scribe lines and at least partially within the junctions of the scribe lines. Each of these metal plates has one or more slots to help relieve the pressure. Alternatively, instead of metal plates, grooves that may be filled with metal could be placed into the scribe lines. These metal plates could also be used concurrently with a seal ring for better protection during sawing.
摘要翻译：提出了一种划线设计，以减少锯切锯片造成的损坏。一个实施例包括位于划线内且至少部分地位于划线内的金属板。这些金属板中的每一个具有一个或多个槽以帮助减轻压力。或者，代替金属板，可以将填充有金属的凹槽放置在划线中。这些金属板也可以与密封环同时使用，以便在锯切期间更好地保护。

45. 发明授权

US07732897B2 Methods of die sawing and structures formed thereby 有权
标题翻译：模具切割的方法和由此形成的结构
公开(公告)号：US07732897B2
公开(公告)日：2010-06-08
申请号：US11424367
申请日：2006-06-15
申请人： Shin-Puu Jeng , Hao-Yi Tsai
发明人： Shin-Puu Jeng , Hao-Yi Tsai
IPC分类号： H01L23/544
CPC分类号： H01L21/78 , B28D5/022
摘要： A structure includes a substrate having a plurality of scribe line areas surrounding a plurality of die areas. Each of the die areas includes at least one first conductive structure formed over the substrate. Each of the scribe line areas includes at least one active region and at least one non-active region. The active region includes a second conductive structure formed therein. The structure further includes at least one first passivation layer formed over the first conductive structure and second conductive structure, wherein at least a portion of the first passivation layer within the non-active region is removed, whereby die-sawing damage is reduced.
摘要翻译：一种结构包括具有围绕多个管芯区域的多个划线区域的衬底。每个管芯区域包括形成在衬底上的至少一个第一导电结构。每个划线区域包括至少一个有效区域和至少一个非有源区域。有源区包括形成在其中的第二导电结构。该结构还包括形成在第一导电结构和第二导电结构之上的至少一个第一钝化层，其中非活性区域内的第一钝化层的至少一部分被去除，从而降低模切锯损坏。

46. 发明申请

US20100117080A1 SEMICONDUCTOR TEST PAD STRUCTURES 有权
公开(公告)号：US20100117080A1
公开(公告)日：2010-05-13
申请号：US12267021
申请日：2008-11-07
申请人： Hsien-Wei Chen , Ying-Ju Chen , Yu-Wen Liu , Hao-Yi Tsai , Shin-Puu Jeng
发明人： Hsien-Wei Chen , Ying-Ju Chen , Yu-Wen Liu , Hao-Yi Tsai , Shin-Puu Jeng
IPC分类号： H01L23/485
CPC分类号： H01L22/34 , H01L24/05 , H01L2924/14 , H01L2924/1461 , H01L2924/00
摘要： A semiconductor test pad interconnect structure with integrated die-separation protective barriers. The interconnect structure includes a plurality of stacked metal layers each having an electrically conductive test pad separated from other test pads by a dielectric material layer. In one embodiment, at least one metallic via bar is embedded into the interconnect structure and electrically interconnects each of the test pads in the metal layers together. The via bar extends substantially along an entire first side defined by each test pad in some embodiments. In other embodiments, a pair of opposing via bars may be provided that are arranged on opposite sides of a die singulation saw cut line defined in a scribe band on a semiconductor wafer.
摘要翻译：具有集成的模具隔离保护屏障的半导体测试焊盘互连结构。互连结构包括多个堆叠的金属层，每个层具有通过介电材料层与其它测试焊盘分离的导电测试焊盘。在一个实施例中，至少一个金属通孔条被嵌入到互连结构中，并将金属层中的每个测试焊盘电连接在一起。在一些实施例中，通孔棒基本上沿着由每个测试垫限定的整个第一侧面延伸。在其他实施例中，可以提供一对相对的通孔条，其布置在限定在半导体晶片上的划线带中的模切单切锯切线的相对侧上。

47. 发明申请

US20090283911A1 Backend Interconnect Scheme with Middle Dielectric Layer Having Improved Strength 有权
标题翻译：后置互连方案与中间介质层具有改进的强度
公开(公告)号：US20090283911A1
公开(公告)日：2009-11-19
申请号：US12121541
申请日：2008-05-15
申请人： Hao-Yi Tsai , Yu-Wen Liu , Hsien-Wei Chen , Ying-Ju Chen , Shin-Puu Jeng
发明人： Hao-Yi Tsai , Yu-Wen Liu , Hsien-Wei Chen , Ying-Ju Chen , Shin-Puu Jeng
IPC分类号： H01L23/522
CPC分类号： H01L21/76835 , H01L23/5222 , H01L23/5329 , H01L24/05 , H01L2224/02166 , H01L2224/05093 , H01L2224/05556 , H01L2924/14 , H01L2924/00
摘要： An integrated circuit structure includes a first, a second and a third metallization layer. The first metallization layer includes a first dielectric layer having a first k value; and first metal lines in the first dielectric layer. The second metallization layer is over the first metallization layer, and includes a second dielectric layer having a second k value greater than the first k value; and second metal lines in the second dielectric layer. The third metallization layer is over the second metallization layer, and includes a third dielectric layer having a third k value; and third metal lines in the third dielectric layer. The integrated circuit structure further includes a bottom passivation layer over the third metallization layer.
摘要翻译：集成电路结构包括第一，第二和第三金属化层。第一金属化层包括具有第一k值的第一介电层; 和第一介电层中的第一金属线。第二金属化层在第一金属化层之上，并且包括具有大于第一k值的第二k值的第二介电层; 和第二介电层中的第二金属线。第三金属化层在第二金属化层之上，并且包括具有第三k值的第三介电层; 和第三介电层中的第三金属线。集成电路结构还包括在第三金属化层上的底部钝化层。

48. 发明申请

US20090011539A1 Flexible Structures for Interconnect Reliability Test 有权
标题翻译：互连可靠性测试的灵活结构
公开(公告)号：US20090011539A1
公开(公告)日：2009-01-08
申请号：US11971072
申请日：2008-01-08
申请人： Shin-Puu Jeng , Shang-Yun Hou , Hao-Yi Tsai , Anbiarshy N.F. Wu
发明人： Shin-Puu Jeng , Shang-Yun Hou , Hao-Yi Tsai , Anbiarshy N.F. Wu
IPC分类号： H01L21/00
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an integrated circuit structure includes forming a test wafer. The step of forming the test wafer includes providing a first semiconductor substrate; and forming a first plurality of unit blocks over the first semiconductor substrate. Each of the first plurality of unit blocks includes a plurality of connection block cells arranged as an array. Each of the connection block cells includes two connection blocks, and a metal line connecting the two connection blocks. The method further includes forming a plurality of unit block boundary lines separating the first plurality of unit blocks from each other; and forming a first plurality of metal lines connecting a portion of the first plurality of unit blocks.
摘要翻译：一种用于形成集成电路结构的方法包括形成测试晶片。形成测试晶片的步骤包括提供第一半导体衬底; 以及在所述第一半导体衬底上形成第一多个单元块。第一多个单元块中的每一个包括被排列成阵列的多个连接块单元。每个连接块单元包括两个连接块和连接两个连接块的金属线。该方法还包括形成将第一多个单元块彼此分开的多个单位块边界线; 以及形成连接所述第一多个单元块的一部分的第一多个金属线。

49. 发明申请

US20080303539A1 Parametric testline with increased test pattern areas 有权
标题翻译：参数测试线具有增加的测试图案区域
公开(公告)号：US20080303539A1
公开(公告)日：2008-12-11
申请号：US11811135
申请日：2007-06-08
申请人： Hsien-Wei Chen , Shih-Hsun Hsu , Hao-Yi Tsai , Shin-Puu Jeng
发明人： Hsien-Wei Chen , Shih-Hsun Hsu , Hao-Yi Tsai , Shin-Puu Jeng
IPC分类号： G01R31/26
CPC分类号： G01R31/2884 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit parametric testline providing increased test pattern areas is disclosed. The testline comprises a dielectric layer over a substrate, a plurality of probe pads over the dielectric layer, and a first device under test (DUT) formed in the testline in a space underlying the probe pads. The testline may also include a second DUT, which is formed in a space underlying the probe pads overlying the first DUT in an overlaying configuration. The testline may further include a polygon shaped probe pad structure providing an increased test pattern area between adjacent probe pads.
摘要翻译：公开了一种提供增加的测试图案区域的集成电路参数测试线。测试线包括衬底上的电介质层，电介质层上的多个探针焊盘，以及形成在探针焊盘下方空间中的测试线中的第一被测器件（DUT）。测试线还可以包括第二DUT，其以覆盖配置形成在覆盖第一DUT的探针焊盘下方的空间中。测试线还可以包括多边形形状的探针焊盘结构，其提供相邻探针焊盘之间增加的测试图案区域。

50. 发明申请

US20080191205A1 Test structure for seal ring quality monitor 有权
标题翻译：密封圈质量监测仪的测试结构
公开(公告)号：US20080191205A1
公开(公告)日：2008-08-14
申请号：US11706940
申请日：2007-02-13
申请人： Hao-Yi Tsai , Shih-Hsun Hsu , Shih-Cheng Chang , Shang-Yun Hou , Hsien-Wei Chen , Chia-Lun Tsai , Benson Liu , Shin-Puu Jeng , Anbiarshy Wu
发明人： Hao-Yi Tsai , Shih-Hsun Hsu , Shih-Cheng Chang , Shang-Yun Hou , Hsien-Wei Chen , Chia-Lun Tsai , Benson Liu , Shin-Puu Jeng , Anbiarshy Wu
IPC分类号： H01L23/58
CPC分类号： H01L23/585 , H01L22/34 , H01L24/11 , H01L2224/0554 , H01L2224/05548 , H01L2224/05573 , H01L2224/05624 , H01L2224/05639 , H01L2224/05647 , H01L2224/05684 , H01L2224/45147 , H01L2224/48091 , H01L2924/00014 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor structure includes a daisy chain adjacent to an edge of a semiconductor chip. The daisy chain includes a plurality of horizontal metal lines distributed in a plurality of metallization layers, wherein the horizontal metal lines are serially connected; a plurality of connecting pads in a same layer and electrically connecting the horizontal metal lines, wherein the connecting pads are physically separated from each other; and a plurality of vertical metal lines, each connecting one of the connecting pads to one of the horizontal metal lines, wherein one of the plurality of connecting pads is connected to one of the plurality of horizontal metal lines by only one of the plurality of vertical metal lines; and a seal ring adjacent and electrically disconnected from the daisy chain.
摘要翻译：半导体结构包括与半导体芯片的边缘相邻的菊花链。菊花链包括分布在多个金属化层中的多个水平金属线，其中水平金属线串联连接; 在相同层中的多个连接焊盘并且电连接水平金属线，其中连接焊盘在物理上彼此分离; 以及多个垂直金属线，每个将所述连接焊盘中的一个连接到所述水平金属线之一，其中所述多个连接焊盘中的一个连接焊盘中的一个连接焊盘仅通过所述多个垂直金属线中的一个垂直连接金属线以及与菊花链相邻且电气断开的密封环。

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