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41. 发明授权

US07009226B1 In-situ nitride/oxynitride processing with reduced deposition surface pattern sensitivity 有权
标题翻译：原位氮化物/氮氧化物处理，沉积表面图案灵敏度降低
公开(公告)号：US07009226B1
公开(公告)日：2006-03-07
申请号：US10887836
申请日：2004-07-12
申请人： Sey-Ping Sun
发明人： Sey-Ping Sun
IPC分类号： H01L29/78
CPC分类号： H01L21/3145 , H01L21/76829 , H01L21/76832 , H01L29/7843 , Y10S257/90
摘要： Carrier mobility in transistor channel regions is increased by depositing a conformal stressed liner. Embodiments include forming a silicon oxynitride layer on the stressed liner to reduce or eliminate deposition surface pattern sensitivity during gap filling, and in-situ SACVD of silicon oxide gap fill directly on the stressed liner with reduced pattern sensitivity. Embodiments also include the use of Si—Ge substrates.
摘要翻译：晶体管沟道区中的载流子迁移率通过沉积保形应力衬垫而增加。实施例包括在应力衬垫上形成氧氮化硅层以减少或消除间隙填充期间的沉积表面图案敏感性，并且以减小的图案灵敏度直接在应力衬垫上填充氧化硅间隙的原位SACVD。实施例还包括使用Si-Ge衬底。

42. 发明申请

US20050247926A1 Semiconductor device based on Si-Ge with high stress liner for enhanced channel carrier mobility 有权
标题翻译：基于具有高应力衬垫的Si-Ge的半导体器件，用于增强通道载流子迁移率
公开(公告)号：US20050247926A1
公开(公告)日：2005-11-10
申请号：US10838330
申请日：2004-05-05
申请人： Sey-Ping Sun , David Brown
发明人： Sey-Ping Sun , David Brown
IPC分类号： H01L21/336 , H01L21/8238 , H01L29/10 , H01L31/072
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823828 , H01L29/1054 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： The carrier mobility in transistor channel regions of Si—Ge devices is increased by employing a stressed liner. Embodiments include applying a high compressive or tensile stressed film overlying relaxed source/drain regions. Other embodiments include applying a high compressively or high tensilely stressed film, after post silicide spacer removal, over gate electrodes and strained Si source/drain regions of P-channel or N-channel transistors, respectively.
摘要翻译： Si-Ge器件的晶体管沟道区域中的载流子迁移率通过使用应力衬里而增加。实施例包括施加覆盖松弛的源极/漏极区域的高压缩或拉伸应力膜。其他实施例包括分别在栅极电极和P沟道或N沟道晶体管的应变Si源极/漏极区之后施加高度压缩或高拉伸应力膜，在硅化物间隔物去除之后。

43. 发明授权

US06257760B1 Using a superlattice to determine the temperature of a semiconductor fabrication process 失效
标题翻译：使用超晶格来确定半导体制造工艺的温度
公开(公告)号：US06257760B1
公开(公告)日：2001-07-10
申请号：US09454070
申请日：1999-12-02
申请人： Bradley M. Davis , Shengnian Davis Song , Sey-Ping Sun
发明人： Bradley M. Davis , Shengnian Davis Song , Sey-Ping Sun
IPC分类号： G01K700
CPC分类号： G01K15/00 , G01K7/186 , H01L21/02381 , H01L21/0245 , H01L21/02491 , H01L21/02507 , H01L21/02532 , H01L22/12
摘要： A method is provided for determining the temperature of a semiconductor fabrication process in which a resistivity versus temperature calibration curve for a superlattice structure is created. A plurality of similar superlattice structures which include alternating layers of a conductor and a semiconductor may be annealed at different temperatures. The resistivity of each superlattice structure may then be measured after the superlattice structures have been cooled to room temperature in order to form the calibration curve. A similar superlattice structure may then be subjected to the temperature at which the semiconductor fabrication process is typically performed, causing the resistivity of the superlattice structure to change. Based on the resulting resistivity of the superlattice structure, the calibration curve may be used to determine the process temperature of the superlattice structure during the fabrication process. The length of time that the superlattice structure is subjected to the process temperature is selected to be the time duration of the process whose temperature is being determined. Once the actual process temperature is known, the temperature controls for the process may be adjusted in an attempt to reach the desired process temperature.
摘要翻译：提供了一种用于确定其中产生超晶格结构的电阻率对温度校准曲线的半导体制造工艺的温度的方法。包括导体和半导体的交替层的多个类似的超晶格结构可以在不同的温度下退火。然后可以在将超晶格结构冷却至室温以便形成校准曲线之后测量每个超晶格结构的电阻率。然后可以将类似的超晶格结构经受通常进行半导体制造工艺的温度，导致超晶格结构的电阻率改变。基于超晶格结构的所得电阻率，校准曲线可用于确定制造过程中超晶格结构的工艺温度。超晶格结构经受处理温度的时间长度被选择为正在确定温度的工艺的持续时间。一旦知道实际的工艺温度，就可以调整工艺的温度控制，以达到所需的工艺温度。

44. 发明授权

US06242367B1 Method of forming silicon nitride films 失效
标题翻译：形成氮化硅膜的方法
公开(公告)号：US06242367B1
公开(公告)日：2001-06-05
申请号：US09352520
申请日：1999-07-13
申请人： Sey-Ping Sun , Minh Van Ngo
发明人： Sey-Ping Sun , Minh Van Ngo
IPC分类号： H01L21469
CPC分类号： C23C16/345 , H01L21/3185
摘要： The present invention is directed to a method of forming process layers comprised of silicon nitride. In one embodiment, the method comprises forming a silicon nitride layer using silane volumes ranging from approximately 350-390 standard cubic centimeters.
摘要翻译：本发明涉及一种形成由氮化硅构成的工艺层的方法。在一个实施方案中，该方法包括使用约350-390标准立方厘米的硅烷体积形成氮化硅层。

45. 发明授权

US6124217A In-situ SiON deposition/bake/TEOS deposition process for reduction of defects in interlevel dielectric for integrated circuit interconnects 有权
标题翻译：用于集成电路互连的用于减少层间电介质缺陷的原位SiON沉积/烘烤/ TEOS沉积工艺
公开(公告)号：US6124217A
公开(公告)日：2000-09-26
申请号：US200016
申请日：1998-11-25
申请人： Sey-Ping Sun , Mark I. Gardner , Minh Van Ngo
发明人： Sey-Ping Sun , Mark I. Gardner , Minh Van Ngo
IPC分类号： C23C16/30 , C23C16/56 , H01L21/314 , H01L21/318 , H01L21/768 , H01L23/522 , H01L29/78 , H01L21/31
CPC分类号： H01L21/76801 , H01L21/3145 , H01L21/76828 , H01L21/76834
摘要： An interlevel dielectric including a tetraethyl orthosilicate (TEOS) oxide and a silicon oxynitride (SiON) etch stop layer is formed for use in integrated circuit fabrication. A SiON layer is deposited onto a semiconductor substrate which may include transistors and/or interconnect levels. The SiON layer is heated before deposition of the TEOS layer. Heating of the SiON layer greatly reduces the number of defects formed during the TEOS deposition. A highly conformal, high-quality interlevel dielectric is thereby formed.
摘要翻译：形成包含原硅酸四乙酯（TEOS）氧化物和氧氮化硅（SiON）蚀刻停止层的层间电介质用于集成电路制造。 SiON层沉积在可包括晶体管和/或互连级别的半导体衬底上。在沉积TEOS层之前加热SiON层。 SiON层的加热大大减少了在TEOS沉积期间形成的缺陷的数量。由此形成高度保形的高品质层间电介质。

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