专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明申请

US20070066056A1 Method of removing a photoresist and method of manufacturing a semiconductor device using the same 审中-公开
标题翻译：去除光致抗蚀剂的方法和使用其制造半导体器件的方法
公开(公告)号：US20070066056A1
公开(公告)日：2007-03-22
申请号：US11447032
申请日：2006-06-06
申请人： Jong-Kyu Kim , Sung-Gil Choi , Jang-Bin Yim , Sang-Dong Kwon , Ki-Jeong Kim
发明人： Jong-Kyu Kim , Sung-Gil Choi , Jang-Bin Yim , Sang-Dong Kwon , Ki-Jeong Kim
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/31138 , G03F7/427 , H01J37/32091 , H01J2237/3342 , H01L27/10808 , H01L27/10852
摘要： Example embodiments of the present invention provide a method of removing a photoresist and a method of manufacturing a semiconductor device using the same. In a method of removing a photoresist and a method of manufacturing a semiconductor device, a plasma including active ions and radicals may be generated. The active ions may be modified into directional active ions. The photoresist may be etched using the directional active ions as main etching factors and/or the radicals as subsidiary etching factors. The photoresist may be completely removed from the semiconductor device such as a lower electrode. Thus, the likelihood of an increase in electrical resistance due to residual photoresist may decrease.
摘要翻译：本发明的示例性实施例提供一种去除光致抗蚀剂的方法和使用其制造半导体器件的方法。在去除光致抗蚀剂的方法和制造半导体器件的方法中，可以产生包括活性离子和自由基的等离子体。活性离子可以被修饰成定向活性离子。可以使用定向活性离子作为主要蚀刻因子和/或自由基作为辅助蚀刻因子来蚀刻光致抗蚀剂。光致抗蚀剂可以从诸如下电极的半导体器件完全去除。因此，残留光致抗蚀剂引起的电阻增加的可能性可能降低。

42. 外观设计

USD529473S1 Mobile phone 有权
公开(公告)号：USD529473S1
公开(公告)日：2006-10-03
申请号：US29236531
申请日：2005-08-18
申请人： Jong-Kyu Kim , Yoon-Young Cho , Jong-Seong Lee , Chang-Hwan Hwang
设计人： Jong-Kyu Kim , Yoon-Young Cho , Jong-Seong Lee , Chang-Hwan Hwang

43. 发明申请

US20060046382A1 Method of forming a capacitor for a semiconductor device 审中-公开
标题翻译：形成用于半导体器件的电容器的方法
公开(公告)号：US20060046382A1
公开(公告)日：2006-03-02
申请号：US11206418
申请日：2005-08-17
申请人： Kuk-Han Yoon , Sang-Sup Jeong , Sung-Gil Choi , Jong-Kyu Kim
发明人： Kuk-Han Yoon , Sang-Sup Jeong , Sung-Gil Choi , Jong-Kyu Kim
IPC分类号： H01L21/8242
CPC分类号： H01L27/10817 , H01L27/10852 , H01L28/91
摘要： In an embodiment, a method of forming a capacitor for a semiconductor device of which structural stability is improved is shown. Cylindrical storage electrodes are formed in a matrix pattern on a substrate that includes an insulation interlayer having contacts therein so that a mold layer surrounds the cylindrical storage electrodes. Sacrificial plugs are formed with a cap within these electrodes. A stabilizing layer is formed on the etched mold layer and the cylindrical storage electrode by partially etching the mold layer. The stabilizing layer is etched until the sacrificial plug is exposed, thereby forming a spacer. While the sacrificial plug and the mold layer are fully removed, the spacer is partially removed, thereby forming a stabilizing member for supporting neighboring storage electrodes adjacent to each other. Accordingly, a structural stability of the capacitor is improved.
摘要翻译：在一个实施例中，示出了形成其结构稳定性提高的半导体器件的电容器的方法。圆柱形存储电极在基板上以矩阵图案形成，该基板包括其中具有触点的绝缘中间层，使得模具层围绕圆柱形存储电极。牺牲塞在这些电极内形成有盖。通过部分蚀刻模具层，在蚀刻的模具层和圆柱形存储电极上形成稳定层。蚀刻稳定层，直到牺牲塞被暴露，从而形成间隔物。尽管完全去除了牺牲塞和模具层，但是间隔件被部分地移除，从而形成用于支撑彼此相邻的相邻存储电极的稳定构件。因此，提高了电容器的结构稳定性。

44. 外观设计

USD725185S1 Printer 有权
公开(公告)号：USD725185S1
公开(公告)日：2015-03-24
申请号：US29461725
申请日：2013-07-26
申请人： Jong-Kyu Kim , Sang-In Lee , Seung-Wook Jeong , Naoto Fukasawa
设计人： Jong-Kyu Kim , Sang-In Lee , Seung-Wook Jeong , Naoto Fukasawa

45. 发明授权

US08987610B2 Vent structure for electromagnetic shielding 有权
标题翻译：通风结构用于电磁屏蔽
公开(公告)号：US08987610B2
公开(公告)日：2015-03-24
申请号：US13466422
申请日：2012-05-08
申请人： Ui-Jung Kim , Kwang-Uk Chu , Jong-Kyu Kim , Dae-Heon Lee
发明人： Ui-Jung Kim , Kwang-Uk Chu , Jong-Kyu Kim , Dae-Heon Lee
IPC分类号： H05K9/00
CPC分类号： H05K9/0041
摘要： A vent structure for electromagnetic shielding includes: a conductive shielding case having a vent formed therein: a conductive shielding duct installed on the shielding case so as to cover the vent, including a space formed perpendicular to the direction of motion of air discharged from the vent to vent the air and a discharge port connected from the space to the outside to discharge the air introduced into the space to the outside, and shielding electromagnetic waves; and an EMI (Electro Magnetic Interference) gasket installed at a bonding surface between the shielding case and the shielding duct, and electrically connecting the shielding case and the shielding duct.
摘要翻译：用于电磁屏蔽的通风结构包括：导电屏蔽壳，其中形成有通风口;导电屏蔽导管，安装在屏蔽壳上，以便覆盖通风口，包括垂直于从通风口排出的空气的运动方向形成的空间排出空气和从该空间连接到外部的排出口，将引入空间的空气排出到外部，并屏蔽电磁波; 以及安装在屏蔽壳体和屏蔽导管之间的接合表面处的EMI（电磁干扰）垫片，并且电连接屏蔽壳体和屏蔽导管。

46. 发明授权

US08927384B2 Methods of fabricating a semiconductor memory device 有权
标题翻译：制造半导体存储器件的方法
公开(公告)号：US08927384B2
公开(公告)日：2015-01-06
申请号：US13400993
申请日：2012-02-21
申请人： Jong-Kyu Kim , Sangsup Jeong , Kukhan Yoon , Junsoo Lee , SungII Cho , Yong-Joon Choi
发明人： Jong-Kyu Kim , Sangsup Jeong , Kukhan Yoon , Junsoo Lee , SungII Cho , Yong-Joon Choi
IPC分类号： H01L21/20 , H01L27/108 , H01L49/02 , H01L27/02 , H01L21/311
CPC分类号： H01L28/91 , H01L21/31144 , H01L27/0203 , H01L27/10817 , H01L27/10852
摘要： A method of fabricating a semiconductor memory device includes forming a hard mask pattern using a damascene method on a lower mold layer stacked on a substrate and etching the lower mold layer using the hard mask pattern as an etch mask to define a protrusion under the hard mask pattern. A support pattern is formed on a top surface of the etched lower mold layer, the top surface of the etched lower mold layer being located at a lower level than a top surface of the protrusion. A lower electrode supported by the support pattern is formed.
摘要翻译：一种制造半导体存储器件的方法包括：使用镶嵌方法在堆叠在衬底上的下模层上形成硬掩模图案，并使用硬掩模图案蚀刻下模层作为蚀刻掩模，以在硬掩模之下限定突起模式。在蚀刻的下模层的顶表面上形成支撑图案，蚀刻的下模层的顶表面位于比突起的顶表面更低的水平。形成由支撑图案支撑的下电极。

47. 发明授权

US08704283B2 Semiconductor devices 有权
标题翻译：半导体器件
公开(公告)号：US08704283B2
公开(公告)日：2014-04-22
申请号：US12724450
申请日：2010-03-16
申请人： Jong-Kyu Kim , Sang-Sup Jeong , Sung-Gil Choi , Heung-Sik Park , Kuk-Han Yoon , Yong-Joon Choi
发明人： Jong-Kyu Kim , Sang-Sup Jeong , Sung-Gil Choi , Heung-Sik Park , Kuk-Han Yoon , Yong-Joon Choi
IPC分类号： H01L27/108
CPC分类号： H01L27/10852 , H01L28/91
摘要： A semiconductor device includes a lower electrode, a supporting member enclosing at least an upper portion of the lower electrode, a dielectric layer on the lower electrode and the supporting member, and an upper electrode disposed on the dielectric layer. The supporting member may have a first portion that extends over an upper part of the sidewall of the lower electrode, and a second portion covering the upper surface of the lower electrode. The first portion of the supporting member protrudes above the lower electrode.
摘要翻译：半导体器件包括下电极，至少包围下电极的上部的支撑构件，下电极上的电介质层和支撑构件，以及设置在电介质层上的上电极。支撑构件可以具有在下电极的侧壁的上部上延伸的第一部分和覆盖下电极的上表面的第二部分。支撑构件的第一部分突出在下电极的上方。

48. 外观设计

USD688742S1 Printer 有权
公开(公告)号：USD688742S1
公开(公告)日：2013-08-27
申请号：US29415211
申请日：2012-03-08
申请人： Min-Chul Kim , Jong-Kyu Kim , Seung-Wook Jeong
设计人： Min-Chul Kim , Jong-Kyu Kim , Seung-Wook Jeong

49. 发明申请

US20120142179A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120142179A1
公开(公告)日：2012-06-07
申请号：US13287345
申请日：2011-11-02
申请人： Jongchul PARK , Jong-Kyu Kim , Ki-jin Park , Sangsup Jeong
发明人： Jongchul PARK , Jong-Kyu Kim , Ki-jin Park , Sangsup Jeong
IPC分类号： H01L21/28 , H01L21/30
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/76816 , H01L21/76897 , H01L27/10855 , H01L27/10894 , H01L28/90
摘要： A method of manufacturing a semiconductor device includes forming a lower film including a cell region and a peripheral circuit region, forming a first sacrificial film on the lower film, the first sacrificial film having trenches in the cell region, forming a second sacrificial pattern on the first sacrificial film, the second sacrificial pattern having line-shaped patterns spaced apart from each other and crossing the trenches in the cell region, and the second sacrificial pattern covering a top surface of the first sacrificial film in the peripheral circuit region, and patterning the first sacrificial film to form upper holes in portions of the trenches exposed by the second sacrificial pattern.
摘要翻译：一种制造半导体器件的方法包括：形成包括单元区域和外围电路区域的下膜，在下膜上形成第一牺牲膜，第一牺牲膜在单元区域中具有沟槽，在第二牺牲膜上形成第二牺牲图案第一牺牲膜，第二牺牲图案具有彼此间隔开并与电池区域中的沟槽交叉的线状图案，并且第二牺牲图案覆盖外围电路区域中的第一牺牲膜的顶表面，并且图案化第一牺牲膜，以在由第二牺牲图案暴露的部分沟槽中形成上孔。

50. 外观设计

USD641395S1 Printer 有权
公开(公告)号：USD641395S1
公开(公告)日：2011-07-12
申请号：US29316761
申请日：2009-10-29
申请人： Ji-Sang Park , Hoon-Tae Kim , Jong-Kyu Kim
设计人： Ji-Sang Park , Hoon-Tae Kim , Jong-Kyu Kim

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式