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41. 发明授权

US07330052B2 Area efficient fractureable logic elements 有权
$Area efficient fractureable logic elements$
标题翻译：区域有效的可断裂逻辑元件
公开(公告)号：US07330052B2
公开(公告)日：2008-02-12
申请号：US11234538
申请日：2005-09-22
申请人： Sinan Kaptanoglu , Bruce B. Pedersen , James G. Schleicher , Jinyong Yuan , Michael D. Hutton , David Lewis
发明人： Sinan Kaptanoglu , Bruce B. Pedersen , James G. Schleicher , Jinyong Yuan , Michael D. Hutton , David Lewis
IPC分类号： G06F7/38 , H03K19/177
CPC分类号： H03K19/1737
摘要： A fracturable logic element includes a first, second, third, and fourth two-input lookup tables (2-LUTs). Each 2-LUT includes four memory elements. Each memory element is configured to hold one data bit. The fracturable logic element also includes a set of six inputs and a control circuit configured to operate in a first mode and a second mode. When the control circuit operates in the first mode, a first combinatorial output is generated using four of the set of six inputs and the first, second, third, and fourth 2-LUTs. When the control circuit operates in the second mode, a second combinatorial output is generated using a first subset of three of the set of six inputs and the first and second 2-LUTs. Additionally, when the control circuit operates in the second mode, a third combinatorial output is generated using a second subset of three of the set of six inputs and the third and fourth 2-LUTs, the first and second subsets being non-intersecting subsets of the set of six inputs.
摘要翻译：可分解逻辑元件包括第一，第二，第三和第四双输入查找表（2-LUT）。每个2-LUT包括四个存储元件。每个存储器元件被配置为保持一个数据位。可分解逻辑元件还包括一组六个输入和被配置为在第一模式和第二模式下操作的控制电路。当控制电路在第一模式下工作时，使用六个输入和第一，第二，第三和第四2-LUT中的四个产生第一组合输出。当控制电路在第二模式下操作时，使用六组输入和第一和第二2-LUT组中的三个的第一子集来生成第二组合输出。另外，当控制电路在第二模式下工作时，使用六组输入和第三和第四2-LUT组中的三个的第二子集来产生第三组合输出，第一和第二子集是不相交的子集一组六个输入。

42. 发明授权

US07312632B2 Fracturable lookup table and logic element 有权
标题翻译：可破坏的查找表和逻辑元素
公开(公告)号：US07312632B2
公开(公告)日：2007-12-25
申请号：US11753048
申请日：2007-05-24
申请人： David Lewis , Bruce Pedersen , Sinan Kaptanoglu , Andy Lee
发明人： David Lewis , Bruce Pedersen , Sinan Kaptanoglu , Andy Lee
IPC分类号： H03K19/173
CPC分类号： H03K19/17728 , H03K19/1737
摘要： A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.
摘要翻译：逻辑元件包括存储器元件，多路复用器和控制器。多路复用器被布置在包括最高级别的多路复用器的级别中，其中连接到存储器元件的输入端和连接到下一级到最高级复用器的输出的输出端和第一级多路复用器，其输入端连接到第二级多路复用器和至少一个输出。控制器连接到多路复用器。在第一操作模式中，所述控制确定所述第一级多路复用器的所述至少一个输出处的第一模式输出，并且在第二操作模式中，所述控制确定多路复用器的选定输出处的多个第二模式输出，第一级多路复用器。

43. 发明申请

US20070222477A1 FRACTURABLE LOOKUP TABLE AND LOGIC ELEMENT 有权
标题翻译：可折叠的表和逻辑元件
公开(公告)号：US20070222477A1
公开(公告)日：2007-09-27
申请号：US11753048
申请日：2007-05-24
申请人： David Lewis , Bruce Pedersen , Sinan Kaptanoglu , Andy Lee
发明人： David Lewis , Bruce Pedersen , Sinan Kaptanoglu , Andy Lee
IPC分类号： H03K19/177
CPC分类号： H03K19/17728 , H03K19/1737
摘要： A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexes with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.
摘要翻译：逻辑元件包括存储器元件，多路复用器和控制器。多路复用器被布置成包括具有连接到存储器元件的输入的最高级复用的输出和连接到下一个到最高级多路复用器的输出的输出以及具有连接到第二级的多路复用器的输出的第一级多路复用器多路复用器和至少一个输出。控制器连接到多路复用器。在第一操作模式中，所述控制确定所述第一级多路复用器的所述至少一个输出处的第一模式输出，并且在第二操作模式中，所述控制确定多路复用器的选定输出处的多个第二模式输出，第一级多路复用器。

44. 发明授权

US06888373B2 Fracturable incomplete look up table for area efficient logic elements 有权
标题翻译：用于区域高效逻辑元素的难以置信的不完整查询表
公开(公告)号：US06888373B2
公开(公告)日：2005-05-03
申请号：US10365647
申请日：2003-02-11
申请人： Sinan Kaptanoglu , David Lewis , Bruce Pedersen
发明人： Sinan Kaptanoglu , David Lewis , Bruce Pedersen
IPC分类号： H03K19/173 , H03K19/177
CPC分类号： H03K19/17748 , H03K19/17728
摘要： Disclosed is a configurable logic circuit that includes at least 6 inputs and at least two outputs. The configurable logic element can carry out only a subset of all 6-input logic functions and, thus, requires a substantially smaller silicon area than a 6-LUT that can perform all 6-input logic functions. Also, the configurable logic circuit can be configured such that a first subset of the inputs drive one of the outputs and a second subset of the inputs drive another output.
摘要翻译：公开了一种可配置逻辑电路，其包括至少6个输入和至少两个输出。可配置逻辑元件只能执行所有6输入逻辑功能的一个子集，因此需要比可执行所有6输入逻辑功能的6-LUT更小的硅面积。而且，可配置逻辑电路可被配置为使得输入的第一子集驱动输出之一，并且输入的第二子集驱动另一输出。

45. 发明申请

US20100156460A1 (N+1) INPUT FLIP-FLOP PACKING WITH LOGIC IN FPGA ARCHITECTURES 有权
标题翻译：（N + 1）在FPGA架构中使用逻辑输入FLOP-FLOP包装
公开(公告)号：US20100156460A1
公开(公告)日：2010-06-24
申请号：US12717315
申请日：2010-03-04
申请人： Sinan Kaptanoglu
发明人： Sinan Kaptanoglu
IPC分类号： H03K19/177
CPC分类号： H03K19/1737 , H03K19/17728
摘要： A logic module and flip-flop includes input multiplexers having data inputs coupled to routing resources. A clock multiplexer has inputs coupled to clock resources, and an output. An input-select multiplexer has a first input coupled to the output of an input multiplexer. A flip-flop has a clock input coupled to the output of the clock multiplexer, and a data output coupled to an input of the input-select multiplexer. A logic module has data inputs coupled to the output of the input select multiplexers. A flip-flop multiplexer is coupled to the data input of the flip-flop, and has inputs input coupled to the output of the first input multiplexer, the data output of the logic module, and a third input coupled to routing resources.
摘要翻译：逻辑模块和触发器包括具有耦合到路由资源的数据输入的输入多路复用器。时钟复用器具有耦合到时钟资源的输入和输出。输入选择多路复用器具有耦合到输入多路复用器的输出的第一输入。触发器具有耦合到时钟复用器的输出的时钟输入和耦合到输入选择多路复用器的输入的数据输出。逻辑模块具有耦合到输入选择多路复用器的输出的数据输入。触发器多路复用器耦合到触发器的数据输入，并具有耦合到第一输入多路复用器的输出，逻辑模块的数据输出和耦合到路由资源的第三输入的输入输入。

46. 发明授权

US07701250B1 (N+1) input flip-flop packing with logic in FPGA architectures 有权
标题翻译：（N + 1）输入触发器封装，具有FPGA架构中的逻辑
公开(公告)号：US07701250B1
公开(公告)日：2010-04-20
申请号：US12360971
申请日：2009-01-28
申请人： Sinan Kaptanoglu
发明人： Sinan Kaptanoglu
IPC分类号： G06F7/38 , H03K19/177
CPC分类号： H03K19/1737 , H03K19/17728
摘要： A logic module and flip-flop includes input multiplexers having data inputs coupled to routing resources. A clock multiplexer has inputs coupled to clock resources, and an output. An input-select multiplexer has a first input coupled to the output of an input multiplexer. A flip-flop has a clock input coupled to the output of the clock multiplexer, and a data output coupled to an input of the input-select multiplexer. A logic module has data inputs coupled to the output of the input select multiplexers. A flip-flop multiplexer is coupled to the data input of the flip-flop, and has inputs input coupled to the output of the first input multiplexer, the data output of the logic module, and a third input coupled to routing resources.
摘要翻译：逻辑模块和触发器包括具有耦合到路由资源的数据输入的输入多路复用器。时钟复用器具有耦合到时钟资源的输入和输出。输入选择多路复用器具有耦合到输入多路复用器的输出的第一输入。触发器具有耦合到时钟复用器的输出的时钟输入和耦合到输入选择多路复用器的输入的数据输出。逻辑模块具有耦合到输入选择多路复用器的输出的数据输入。触发器多路复用器耦合到触发器的数据输入，并具有耦合到第一输入多路复用器的输出，逻辑模块的数据输出和耦合到路由资源的第三输入的输入输入。

47. 发明授权

US07545169B1 FPGA architecture having two-level cluster input interconnect scheme without bandwidth limitation 有权
标题翻译：具有两级集群输入互连方案的FPGA架构，无带宽限制
公开(公告)号：US07545169B1
公开(公告)日：2009-06-09
申请号：US12173225
申请日：2008-07-15
申请人： Wenyi Feng , Sinan Kaptanoglu
发明人： Wenyi Feng , Sinan Kaptanoglu
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K19/17736
摘要： An interconnect architecture for a programmable logic device comprises a plurality of interconnect routing lines. The data inputs of a plurality of first-level multiplexers are connected to the plurality of interconnect routing lines such that each interconnect routing line is connected to only one multiplexer. A plurality of second-level multiplexers are organized into multiplexer groups. Each of a plurality of lookup tables is associated with one of the multiplexer groups and has a plurality of lookup table inputs. Each lookup table input is coupled to the output of a different one of the second-level multiplexers in the one of the multiplexer groups with which it is associated. The data inputs of the second-level multiplexers are connected to the outputs of the first-level multiplexers such that each output of each first-level multiplexer is connected to an input of only one second-level multiplexer in each multiplexer group.
摘要翻译：用于可编程逻辑器件的互连架构包括多个互连路由线。多个第一级复用器的数据输入连接到多个互连路由线，使得每个互连路由线仅连接到一个多路复用器。多个第二级多路复用器被组织成多路复用器组。多个查找表中的每一个与多路复用器组中的一个相关联并且具有多个查找表输入。每个查找表输入耦合到与其相关联的多路复合器组中的一个中的不同的一个二级多路复用器的输出。第二级复用器的数据输入连接到第一级复用器的输出，使得每个第一级多路复用器的每个输出连接到每个多路复用器组中仅一个第二级多路复用器的输入。

48. 发明申请

US20080136449A1 Dedicated crossbar and barrel shifter block on programmable logic resources 有权
公开(公告)号：US20080136449A1
公开(公告)日：2008-06-12
申请号：US12069830
申请日：2008-02-12
申请人： Michael Hutton , Sinan Kaptanoglu
发明人： Michael Hutton , Sinan Kaptanoglu
IPC分类号： H03K19/173 , G06F7/00
CPC分类号： H03K19/17736 , G06F5/01
摘要： A dedicated hardware block is provided for implementing crossbars and/or barrel shifters in programmable logic resources. Crossbar and/or barrel shifter circuitry may replace one or more rows, one or more columns, one or more rectangles, or any combination thereof of programmable logic regions on a programmable logic resource. The functionality of the crossbar and/or barrel shifter circuitry can further be improved by implementing time-multiplexing.

49. 发明申请

US20080136446A1 BLOCK LEVEL ROUTING ARCHITECTURE IN A FIELD PROGRAMMABLE GATE ARRAY 失效
标题翻译：在现场可编程门阵列中的块级路由架构
公开(公告)号：US20080136446A1
公开(公告)日：2008-06-12
申请号：US12034555
申请日：2008-02-20
申请人： Sinan Kaptanoglu
发明人： Sinan Kaptanoglu
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H01L27/11803
摘要： An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16×16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. On each of the four sides of the B16×16 tile, and also associated with each of the I/O blocks is a freeway routing channel. A B16×16 tile in the middle level of hierarchy is a sixteen by sixteen array of B1 blocks. The routing resources in the middle level of hierarchy is are expressway routing channels M1, M2, and M3 including groups of interconnect conductors. At the lowest level of the semi-hierarchical FPGA architecture, there are block connect (BC) routing channels, local mesh (LM) routing channels, and direct connect (DC) interconnect conductors. Each BC routing channel is coupled to an expressway tab to provide access for each B1 block to the expressway routing channels M1, M2, and M3, respectively. Each BC routing channel has nine interconnect conductors which are grouped into three groups of three interconnect conductors. Each group of three interconnect conductors is connected to a first side of a Extension Board (EB) 3×3 switch matrix. A second side of each EB 3×3 switch matrix is coupled to the E-tab. Between adjacent B1 blocks, in both the horizontal and vertical directions, the leads on the second side of a first EB 3×3 switch matrix may be coupled to the leads on the second side of second EB3×3 switch matrix by BC criss-cross extension.
摘要翻译： FPGA架构具有顶级，中级和低级。该体系结构的顶层是排列成矩形阵列并由外围的I / O块包围的B16x16瓦数组。在B16x16瓦片的四面中，每个I / O块也与高速公路路由通道相关联。中层层次的B16x16瓦片是16块16块阵列。中层层次中的路由资源是包括互连导体组的高速公路路由信道M 1，M 2和M 3。在半层次FPGA架构的最底层，有块连接（BC）路由通道，局域网（LM）路由通道和直接连接（DC）互连导线。每个BC路由信道被耦合到高速公路标签，以分别向高速公路路由信道M 1，M 2和M 3提供每个B1块的接入。每个BC路由信道具有九个互连导体，它们分成三组三个互连导体。每组三个互连导体连接到扩展板（EB）3x3开关矩阵的第一侧。每个EB 3x3开关矩阵的第二面耦合到E-tab。在相邻B1块之间，在水平和垂直方向上，第一EB 3×3开关矩阵的第二侧上的引线可以通过BC交叉扩展耦合到第二EB3×3开关矩阵的第二侧上的引线。

50. 发明授权

US07385421B2 Block symmetrization in a field programmable gate array 有权
标题翻译：在现场可编程门阵列中的块对称
公开(公告)号：US07385421B2
公开(公告)日：2008-06-10
申请号：US11748865
申请日：2007-05-15
申请人： Sinan Kaptanoglu
发明人： Sinan Kaptanoglu
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17728 , H03K19/1778 , H03K19/17796
摘要： An FPGA architecture has top, middle and low levels. The top level is an array of B16×16 tiles enclosed by I/O blocks. The routing resources in the middle level are expressway routing channels including interconnect conductors. At the lowest level, there are block connect routing channels, local mesh routing channels, and direct connect interconnect conductors to connect the logic elements to further routing resources. Each B1 block includes four clusters of devices. Each of the clusters includes first and second LUT3s, a LUT2, and a DFF. Each of the LUT3s have three inputs and one output. Each of the LUT2s have two inputs and one output. Each DFF has a data input and a data output. In each of the clusters the outputs of the LUT3s are multiplexed to the input of DFF, and symmetrized with the output of the DFF to form two outputs of each of the clusters.
摘要翻译： FPGA架构具有顶级，中级和低级。顶级是由I / O块包围的B16x16瓦数组。中间路由资源是高速公路路由信道，包括互连导体。在最底层，有块连接路由通道，本地网状路由通道和直接连接互连导体，以将逻辑元件连接到更多的路由资源。每个B 1块包括四组设备。每个簇包括第一和第二LUT 3 s，LUT 2和DFF。 LUT 3中的每一个具有三个输入和一个输出。 LUT 2中的每一个具有两个输入和一个输出。每个DFF都有数据输入和数据输出。在每个簇中，LUT 3的输出被复用到DFF的输入，并且与DFF的输出对称，以形成每个簇的两个输出。

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