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41. 发明授权

US4691304A Semiconductor device having an arrangement for preventing operational errors 失效
标题翻译：具有用于防止操作错误的装置的半导体装置
公开(公告)号：US4691304A
公开(公告)日：1987-09-01
申请号：US739092
申请日：1985-05-30
申请人： Ryoichi Hori , Kiyoo Itoh
发明人： Ryoichi Hori , Kiyoo Itoh
IPC分类号： G11C11/413 , G05F3/20 , G06F1/26 , G11C7/02 , G11C11/407 , G11C11/408 , H01L27/02 , H02M3/07 , G11C7/00
CPC分类号： H01L27/0218 , G05F3/205 , H02M3/07
摘要： This invention relates to a semiconductor device formed on a semiconductor chip which is provided with at least a voltage transformation arrangement for transforming an external power supply voltage into an internal power supply voltage. At least a portion of circuits formed in the chip operate by using the internal power supply voltage rather than the external power supply voltage. Semiconductor devices, in particular DRAMs (dynamic random access memories), in which said internal power supply voltage is supplied are controlled so that the starting time of the internal power supply voltage at the moment of the switch-on of the external power supply is later than the starting time of the external power supply voltage, and/or the time necessary for the internal power supply voltage to increase to a predetermined operational level at said moment is longer than that required for said external power supply voltage to increase to a predetermined operational level.
摘要翻译：本发明涉及形成在半导体芯片上的半导体器件，该半导体器件至少具有用于将外部电源电压变换为内部电源电压的电压变换装置。芯片中形成的至少一部分电路通过使用内部电源电压而不是外部电源电压来工作。控制提供所述内部电源电压的半导体装置，特别是DRAM（动态随机存取存储器），使得外部电源的接通时的内部电源电压的起始时间稍晚比外部电源电压的开始时间和/或内部电源电压在所述时刻增加到预定操作电平所需的时间长于所述外部电源电压所需的时间增加到预定的操作水平。

42. 发明授权

US4590588A Monolithic semiconductor memory 失效
标题翻译：单片半导体存储器
公开(公告)号：US4590588A
公开(公告)日：1986-05-20
申请号：US515519
申请日：1983-07-20
申请人： Kiyoo Itoh , Ryoichi Hori
发明人： Kiyoo Itoh , Ryoichi Hori
IPC分类号： G11C5/06 , G11C7/10 , G11C7/18 , G11C5/02
CPC分类号： G11C7/18 , G11C5/063 , G11C7/10 , G11C7/1006
摘要： A semiconductor memory is disclosed having data lines divided lengthwise, which data lines cross word lines in a memory cell array and are selectively coupled to memory cells. A plurality of second data lines are arranged, one for each of predetermined groups of the data lines, to exchange data through first switches. Also one or more third data lines are arranged orthogonally to the second data lines to exchange data with the second data lines through second switches. Read/write controllers are coupled to the third data lines. Data is read and written for desired memory cells by selective drive of the word lines and the first and second switches.
摘要翻译：公开了半导体存储器，其具有纵向分割的数据线，哪些数据线与存储单元阵列中的字线交叉并且选择性地耦合到存储器单元。布置多个第二数据线，每个数据线的预定组中的每一个通过第一开关交换数据。还有一个或多个第三数据线与第二数据线正交地布置，以通过第二开关与第二数据线交换数据。读/写控制器耦合到第三条数据线。通过选择性地驱动字线和第一和第二开关来读取和写入所需存储单元的数据。

43. 发明授权

US06970391B2 Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions 失效
标题翻译：内置电源的半导体器件用于补偿工作条件和制造工艺条件的偏差
公开(公告)号：US06970391B2
公开(公告)日：2005-11-29
申请号：US10441207
申请日：2003-05-20
申请人： Takao Watanabe , Ryoichi Hori , Goro Kitsukawa , Yoshiki Kawajiri , Takayuki Kawahara , Kiyoo Itoh
发明人： Takao Watanabe , Ryoichi Hori , Goro Kitsukawa , Yoshiki Kawajiri , Takayuki Kawahara , Kiyoo Itoh
IPC分类号： G11C5/14 , G11C7/00 , G11C7/12 , G11C8/00 , G11C8/10 , G11C11/4094 , H03K5/08 , H03K17/00 , H03K17/693 , H03K19/003 , H03K19/017 , H03K19/0175 , H03K19/0944 , G11C7/04 , G11C7/02 , G11C11/34
CPC分类号： G11C7/12 , G11C5/14 , G11C5/147 , G11C8/10 , G11C11/4094 , G11C11/413 , H03K5/08 , H03K17/693 , H03K19/00376 , H03K19/00384 , H03K19/017 , H03K19/01707 , H03K19/017518 , H03K19/09448 , H03K2217/0036
摘要： A semiconductor integrated circuit comprises a semiconductor chip, a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on the semiconductor chip, a power supply circuit provided on the semiconductor chip for transforming an external power supply voltage received from the power supply terminal for supplying a source voltage resulting from the voltage transformation to the internal circuit, and a control circuit provided on the semiconductor chip for controlling the power supply circuit, wherein the control circuit includes external power supply voltage detecting means and/or temperature detecting means and responds to the signal from the external power supply voltage detecting means and/or the temperature detecting means by changing the power supply voltage to the internal circuit to thereby maintain the operating speed of the internal circuit to be constant.
摘要翻译：半导体集成电路包括半导体芯片，设置在半导体芯片上用于接收来自外部电源的电压的电源端子，设置在半导体芯片上的内部电路，设置在半导体芯片上的电源电路，用于将从所述电源端子接收用于向所述内部电路提供由所述电压变换产生的源极电压的外部电源电压;以及控制电路，设置在所述半导体芯片上用于控制所述电源电路，其中，所述控制电路包括外部电源电压检测装置和/或温度检测装置，通过改变对内部电路的电源电压来响应来自外部电源电压检测装置和/或温度检测装置的信号，从而将内部电路的操作速度保持为不变。

44. 发明授权

US06740958B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US06740958B2
公开(公告)日：2004-05-25
申请号：US10115101
申请日：2002-04-04
申请人： Shinji Nakazato , Hideaki Uchida , Yoshikazu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
发明人： Shinji Nakazato , Hideaki Uchida , Yoshikazu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
IPC分类号： H01L2900
CPC分类号： H01L27/0623 , H01L27/0214 , H01L27/0218 , H01L27/0922 , H01L27/105 , H01L27/10805
摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.
摘要翻译：公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域，在另一。

45. 发明授权

US06404239B1 Semiconductor integrated circuit device having power reduction mechanism 失效
标题翻译：具有功率降低机构的半导体集成电路装置
公开(公告)号：US06404239B1
公开(公告)日：2002-06-11
申请号：US09613594
申请日：2000-07-10
申请人： Takayuki Kawahara , Ryoichi Hori , Masashi Horiguchi , Ryoichi Kurihara , Kiyoo Itoh , Masakazu Aoki , Takeshi Sakata , Kunio Uchiyama
发明人： Takayuki Kawahara , Ryoichi Hori , Masashi Horiguchi , Ryoichi Kurihara , Kiyoo Itoh , Masakazu Aoki , Takeshi Sakata , Kunio Uchiyama
IPC分类号： H03K1920
CPC分类号： H03K3/356113 , H01L27/0218 , H03K19/0016
摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.
摘要翻译：半导体集成电路器件由各自设置有至少两个MOS晶体管的逻辑门组成。逻辑门连接到第一电势点和第二电位点。半导体集成电路装置包括连接在逻辑门与第一电位点之间和/或逻辑门与第二电势点之间的电流控制装置，用于根据操作状态控制在逻辑门中流动的电流的值逻辑门。该电路可用于在高功耗模式和低功耗模式之间循环运行的器件，例如具有用于功率降低的操作模式和低功率备用或睡眠模式的微处理器。

46. 发明授权

US6125075A Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions 失效
公开(公告)号：US6125075A
公开(公告)日：2000-09-26
申请号：US168998
申请日：1998-10-09
申请人： Takao Watanabe , Ryoichi Hori , Goro Kitsukawa , Yoshiki Kawajiri , Takayuki Kawahara , Kiyoo Itoh
发明人： Takao Watanabe , Ryoichi Hori , Goro Kitsukawa , Yoshiki Kawajiri , Takayuki Kawahara , Kiyoo Itoh
IPC分类号： G11C5/14 , G11C7/00 , G11C7/12 , G11C8/00 , G11C8/10 , G11C11/4094 , H03K5/08 , H03K17/00 , H03K17/693 , H03K19/003 , H03K19/017 , H03K19/0175 , H03K19/0944
CPC分类号： G11C7/12 , G11C11/4094 , G11C11/413 , G11C5/14 , G11C5/147 , G11C8/10 , H03K17/693 , H03K19/00376 , H03K19/00384 , H03K19/017 , H03K19/01707 , H03K19/017518 , H03K19/09448 , H03K5/08 , H03K2217/0036
摘要： A semiconductor integrated circuit comprises a semiconductor chip, a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on the semiconductor chip, a power supply circuit provided on the semiconductor chip for transforming an external power supply voltage received from the power supply terminal for supplying a source voltage resulting from the voltage transformation to the internal circuit, and a control circuit provided on the semiconductor chip for controlling the power supply circuit, wherein the control circuit includes external power supply voltage detecting means and/or temperature detecting means and responds to the signal from the external power supply voltage detecting means and/or the temperature detecting means by changing the power supply voltage to the internal circuit to thereby maintain the operating speed of the internal circuit to be constant.

47. 发明授权

US5587952A Dynamic random access memory including read preamplifiers activated before rewrite amplifiers 失效
标题翻译：动态随机存取存储器包括在重写放大器之前激活的读前置放大器
公开(公告)号：US5587952A
公开(公告)日：1996-12-24
申请号：US391537
申请日：1995-02-21
申请人： Goro Kitsukawa , Takao Watanabe , Ryoichi Hori , Noriyuki Honma , Kunihiko Yamaguchi , Kiyoo Itoh
发明人： Goro Kitsukawa , Takao Watanabe , Ryoichi Hori , Noriyuki Honma , Kunihiko Yamaguchi , Kiyoo Itoh
IPC分类号： G11C11/408 , G11C11/4091 , G11C11/4096 , G11C11/409 , G11C7/06
CPC分类号： G11C11/4087 , G11C11/4082 , G11C11/4091 , G11C11/4096
摘要： A dynamic random access memory is provided which includes word lines for accessing memory cells, data lines for transferring information from the memory cells, and rewrite amplifiers connected to the data lines for rewriting the information to corresponding memory cells. Read pre-amplifiers are also provided for sensing the information, together with common data lines for transferring output signals of the read pre-amplifiers. Each of the read pre-amplifiers has two insulated gate field-effect transistors, gates of which are connected to the data lines, and sources/drains of which are connected with the common data lines, such that the common data lines do not form current paths with the data lines. In addition, the read pre-amplifiers are activated before the rewrite amplifiers.
摘要翻译：提供了一种动态随机存取存储器，其包括用于访问存储单元的字线，用于从存储器单元传送信息的数据线，以及连接到数据线的重写放大器，用于将信息重写到相应的存储器单元。还提供读取前置放大器用于感测信息，以及公共数据线，用于传输读取的前置放大器的输出信号。每个读取的预放大器具有两个绝缘栅场效应晶体管，其栅极连接到数据线，并且其源极/漏极与公共数据线连接，使得公共数据线不形成电流路径与数据线。此外，读取的前置放大器在重写放大器之前被激活。

48. 发明授权

US5386135A Semiconductor CMOS memory device with separately biased wells 失效
标题翻译：半导体CMOS存储器件具有单独偏置的阱
公开(公告)号：US5386135A
公开(公告)日：1995-01-31
申请号：US229340
申请日：1994-04-12
申请人： Shinji Nakazato , Hideaki Uchida , Yoshikazu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
发明人： Shinji Nakazato , Hideaki Uchida , Yoshikazu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
IPC分类号： H01L27/02 , H01L27/06 , H01L27/092 , H01L27/105 , H01L27/108 , H01L29/78
CPC分类号： H01L27/10805 , H01L27/0214 , H01L27/0623 , H01L27/0922 , H01L27/0218 , H01L27/105 , Y10S257/901 , Y10S257/904
摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.
摘要翻译：公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域，在另一。

49. 发明授权

US5377156A Semiconductor device incorporating main and stand-by boosted internal power supply for compensating for deviation on operating condition and fabrication process conditions 失效
标题翻译：采用主要和待机增强内部电源的半导体器件，用于补偿工作条件和制造工艺条件的偏差
公开(公告)号：US5377156A
公开(公告)日：1994-12-27
申请号：US985076
申请日：1992-12-03
申请人： Takao Watanabe , Ryoichi Hori , Goro Kitsukawa , Yoshiki Kawajiri , Takayuki Kawahara , Kiyoo Itoh
发明人： Takao Watanabe , Ryoichi Hori , Goro Kitsukawa , Yoshiki Kawajiri , Takayuki Kawahara , Kiyoo Itoh
IPC分类号： G11C5/14 , G11C7/00 , G11C7/12 , G11C8/00 , G11C8/10 , G11C11/4094 , H03K5/08 , H03K17/00 , H03K17/693 , H03K19/003 , H03K19/017 , H03K19/0175 , H03K19/0944
CPC分类号： G11C7/12 , G11C11/4094 , G11C11/413 , G11C5/14 , G11C5/147 , G11C8/10 , H03K17/693 , H03K19/00376 , H03K19/00384 , H03K19/017 , H03K19/01707 , H03K19/017518 , H03K19/09448 , H03K5/08 , H03K2217/0036
摘要： A semiconductor integrated circuit comprises a semiconductor chip, a power supply terminal provided on the semiconductor chip for receiving a voltage from an external power supply source, an internal circuit provided on the semiconductor chip, a power supply circuit provided on the semiconductor chip for transforming an external power supply voltage received from the power supply terminal for supplying a source voltage resulting from the voltage transformation to the internal circuit, and a control circuit provided on the semiconductor chip for controlling the power supply circuit, wherein the control circuit includes external power supply voltage detecting means and/or temperature detecting means and responds to the signal from the external power supply voltage detecting means and/or the temperature detecting means by changing the power supply voltage to the internal circuit to thereby maintain the operating speed of the internal circuit to be constant.
摘要翻译：半导体集成电路包括半导体芯片，设置在半导体芯片上用于接收来自外部电源的电压的电源端子，设置在半导体芯片上的内部电路，设置在半导体芯片上的电源电路，用于将从所述电源端子接收用于向所述内部电路提供由所述电压变换产生的源极电压的外部电源电压;以及控制电路，设置在所述半导体芯片上用于控制所述电源电路，其中，所述控制电路包括外部电源电压检测装置和/或温度检测装置，通过改变对内部电路的电源电压来响应来自外部电源电压检测装置和/或温度检测装置的信号，从而将内部电路的操作速度保持为不变。

50. 发明授权

US5148255A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5148255A
公开(公告)日：1992-09-15
申请号：US645351
申请日：1991-01-23
申请人： Shinji Nakazato , Hideaki Uchida , Yoshikazu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
发明人： Shinji Nakazato , Hideaki Uchida , Yoshikazu Saito , Masahiro Yamamura , Yutaka Kobayashi , Takahide Ikeda , Ryoichi Hori , Goro Kitsukawa , Kiyoo Itoh , Nobuo Tanba , Takao Watanabe , Katsuhiro Shimohigashi , Noriyuki Homma
IPC分类号： H01L27/02 , H01L27/06 , H01L27/092 , H01L27/105 , H01L27/108
CPC分类号： H01L27/10805 , H01L27/0214 , H01L27/0623 , H01L27/0922 , H01L27/0218 , H01L27/105
摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.
摘要翻译：公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域，在另一。

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