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41. 发明授权

US08514611B2 Memory with low voltage mode operation 有权
标题翻译：内存低电压模式运行
公开(公告)号：US08514611B2
公开(公告)日：2013-08-20
申请号：US12850533
申请日：2010-08-04
申请人： Huy B. Nguyen , Troy L. Cooper , Ravindraraj Ramaraju , Andrew C. Russell
发明人： Huy B. Nguyen , Troy L. Cooper , Ravindraraj Ramaraju , Andrew C. Russell
IPC分类号： G11C11/00
CPC分类号： G11C11/417
摘要： A memory comprising memory cells wherein the memory is configured to operate in a normal voltage mode and a low voltage mode. The method includes during the normal voltage mode, operating the memory cells at a first voltage across each of the memory cells. The method further includes upon transitioning from the normal voltage mode to the low voltage mode, operating the memory cells at a second voltage across each of the memory cells, wherein the second voltage is lower than the first voltage. The method further includes performing an access on a subset of the memory cells while maintaining the second voltage across the memory cells.
摘要翻译：一种存储器，包括存储器单元，其中存储器被配置为在正常电压模式和低电压模式下操作。该方法包括在正常电压模式期间，以每个存储器单元的第一电压操作存储器单元。该方法还包括在从正常电压模式转换到低电压模式时，在每个存储单元上以第二电压操作存储单元，其中第二电压低于第一电压。该方法还包括在保持存储器单元两端的第二电压的同时对存储器单元的子集执行访问。

42. 发明授权

US09081719B2 Selective memory scrubbing based on data type 有权
标题翻译：基于数据类型的选择性内存擦除
公开(公告)号：US09081719B2
公开(公告)日：2015-07-14
申请号：US13588194
申请日：2012-08-17
申请人： Ravindraraj Ramaraju , William C. Moyer , Andrew C. Russell
发明人： Ravindraraj Ramaraju , William C. Moyer , Andrew C. Russell
IPC分类号： G06F12/00 , G06F12/12
CPC分类号： G06F12/12 , G06F12/0893 , G06F2212/1036 , Y02D10/13
摘要： A method for minimizing soft error rates within caches by controlling a memory scrubbing rate selectively for a cache memory at an individual bank level. More specifically, the disclosure relates to maintaining a predetermined sequence and process of storing all modified information of a cache in a subset of ways of the cache, based upon for example, a state of a modified indication within status information of a cache line. A cache controller includes a memory scrubbing controller which is programmed to scrub the subset of the ways with the modified information at a smaller interval (i.e., more frequently) compared to the rest of the ways with clean information (i.e., information where the information stored within the main memory is coherent with the information stored within the cache).
摘要翻译：一种通过有选择地为单个存储体级别的高速缓存存储器控制存储器擦除速率来最小化高速缓存内的软错误率的方法。更具体地，本公开涉及基于例如高速缓存行的状态信息内的修改指示的状态来维持预定顺序和将高速缓存的所有修改信息存储在高速缓存的方式的子集中的处理。高速缓冲存储器控制器包括一个存储器擦除控制器，该存储器擦除控制器被编程为与具有干净信息的其余方式（即，存储信息的信息相比较）以更小的间隔（即，更频繁地）用修改的信息擦除子集的子集在主存储器内部与缓存中存储的信息相干）。

43. 发明申请

US20120230126A1 MEMORY VOLTAGE REGULATOR WITH LEAKAGE CURRENT VOLTAGE CONTROL 有权
标题翻译：具有漏电流电压控制的存储电压调节器
公开(公告)号：US20120230126A1
公开(公告)日：2012-09-13
申请号：US13045294
申请日：2011-03-10
申请人： Ravindraraj Ramaraju , Shayan Zhang , Kenneth R. Burch , Charles E. Seaberg , Andrew C. Russell
发明人： Ravindraraj Ramaraju , Shayan Zhang , Kenneth R. Burch , Charles E. Seaberg , Andrew C. Russell
IPC分类号： G11C5/14 , G11C7/14 , G11C7/00
CPC分类号： G11C11/417 , G11C5/147 , G11C11/412 , G11C29/021 , G11C29/028
摘要： A voltage regulator for a memory that regulates a voltage provided to the memory cells based on a measured leakage current from a second set of memory cells. In one embodiment, based on the measured leakage current, the voltage to the cells is raised or lowered to control the amount of leakage current from the cells.
摘要翻译：一种用于存储器的电压调节器，其基于来自第二组存储器单元的测量的泄漏电流来调节提供给存储器单元的电压。在一个实施例中，基于测量的漏电流，提高或降低对电池的电压以控制来自电池的泄漏电流的量。

44. 发明授权

US09542334B2 Memory management unit TAG memory with CAM evaluate signal 有权
标题翻译：具有CAM评估信号的存储器管理单元TAG存储器
公开(公告)号：US09542334B2
公开(公告)日：2017-01-10
申请号：US13213831
申请日：2011-08-19
申请人： Ravindraraj Ramaraju
发明人： Ravindraraj Ramaraju
IPC分类号： G06F12/10 , G06F9/38
CPC分类号： G06F12/1027 , G06F9/355 , G06F9/3824 , G06F9/3832 , G11C15/04
摘要： A method and data processing system for accessing an entry in a memory array by placing a tag memory unit (114) in parallel with an operand adder circuit (112) to enable tag lookup and generation of speculative way hit/miss information (126) directly from the operands (111, 113) without using the output sum of the operand adder. PGZ-encoded address bits (0:51) from the operands (111, 113) are applied with a carry-out value (Cout48) to a content-addressable memory array (114) having compact bitcells with embedded partial A+B=K logic to generate two speculative hit/miss signals under control of a delayed evaluate signal. A sum value (EA51) computed from the least significant base and offset address bits determines which of the speculative hit/miss signals is selected for output (126).
摘要翻译：一种方法和数据处理系统，用于通过将标记存储器单元（114）与操作数加法器电路（112）并行放置来访问存储器阵列中的入口，以使标签查找和直接产生投机方式命中/未命中信息（126）不使用操作数加法器的输出和从操作数（111,113）中读出。来自操作数（111,113）的PGZ编码的地址位（0:51）被带有进位值（Cout48）到具有嵌入的部分A + B = K的紧凑位单元的内容寻址存储器阵列（114）在延迟评估信号的控制下产生两个投机命中/未命中信号的逻辑。从最低有效基址和偏移地址位计算的和值（EA51）确定选择哪种推测性命中/未命中信号用于输出（126）。

45. 发明授权

US09318158B2 Non-volatile memory using bi-directional resistive elements 有权
标题翻译：使用双向电阻元件的非易失性存储器
公开(公告)号：US09318158B2
公开(公告)日：2016-04-19
申请号：US14287463
申请日：2014-05-27
申请人： Frank K. Baker, Jr. , Perry H. Pelley , Ravindraraj Ramaraju
发明人： Frank K. Baker, Jr. , Perry H. Pelley , Ravindraraj Ramaraju
IPC分类号： G11C11/00 , G11C5/06 , G11C13/00
CPC分类号： G11C5/06 , G11C5/025 , G11C5/063 , G11C5/14 , G11C13/0004 , G11C13/0011 , G11C13/0021 , G11C13/0023 , G11C13/0026 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0073 , G11C2213/74 , G11C2213/79 , G11C2213/82
摘要： A memory cell includes a first bi-directional resistive element having a cathode coupled to a first power rail and an anode coupled to an internal node, a second bi-directional resistive element having a cathode coupled to the internal node and an anode coupled to a second power rail, and a first transistor having a control electrode coupled to the internal node, a first current electrode coupled to a first bitline, and a second current electrode coupled to a third power rail.
摘要翻译：存储单元包括具有耦合到第一电源轨的阴极和耦合到内部节点的阳极的第一双向电阻元件，具有耦合到内部节点的阴极和耦合到内部节点的阳极的第二双向电阻元件第二电源轨，以及具有耦合到所述内部节点的控制电极的第一晶体管，耦合到第一位线的第一电流电极和耦合到第三电力轨的第二电流电极。

46. 发明授权

US08677205B2 Hierarchical error correction for large memories 有权
标题翻译：大存储器的分层纠错
公开(公告)号：US08677205B2
公开(公告)日：2014-03-18
申请号：US13045307
申请日：2011-03-10
申请人： Ravindraraj Ramaraju , Edmund J. Gieske , David F. Greenberg
发明人： Ravindraraj Ramaraju , Edmund J. Gieske , David F. Greenberg
IPC分类号： H03M13/00
CPC分类号： G06F11/1064 , G11C2029/0411
摘要： A mechanism is provided for detecting and correcting a first number of bit errors in a segment of data stored in a memory region being read, while concurrently detecting the presence of higher numbers of bit errors in that segment of data. In the event of detection of a higher number of bit errors in any single segment of data of the memory region, error correction of that higher number of bit errors is performed on the memory region, while concurrently detecting the presence of an even higher level of bit errors. By performing error correction of higher levels of bit errors in such a hierarchical order, memory latency associated with such error correction can be avoided in the majority of data accesses, thereby improving performance of the data access.
摘要翻译：提供了一种用于检测和校正存储在正在读取的存储器区域中的数据段中的第一数量的位错误的机制，同时检测该数据段中是否存在较高数量的位错误。在存储器区域的任何单个数据段中检测到较高数量的位错误的情况下，对存储器区域执行该更高数量的位错误的错误校正，同时检测存在更高级别的位错误。通过以这样的分级顺序执行更高级别的比特错误的纠错，可以在大多数数据访问中避免与这种纠错相关联的存储器等待时间，从而提高数据访问的性能。

47. 发明授权

US08587356B2 Recoverable and reconfigurable pipeline structure for state-retention power gating 有权
标题翻译：用于状态保持功率门控的可恢复和可重新配置的管道结构
公开(公告)号：US08587356B2
公开(公告)日：2013-11-19
申请号：US13403597
申请日：2012-02-23
申请人： Shayan Zhang , William C. Moyer , Ravindraraj Ramaraju
发明人： Shayan Zhang , William C. Moyer , Ravindraraj Ramaraju
IPC分类号： H03K3/00
CPC分类号： H03K3/35606 , H03K3/356008
摘要： A system, electronic circuit, and method are disclosed. A method embodiment comprises receiving a control signal associated with a power gating operation mode of an electronic circuit, applying a reference voltage to the electronic circuit based upon the power gating operation mode, and maintaining data representing a state of a logic stage of the electronic circuit based upon the power gating operation mode. Maintaining comprises, in the described embodiment, storing data of a state of a first logic stage of the electronic circuit within a first storage element in a first power gating operation mode, and recovering data of a state of a second logic stage of the electronic circuit utilizing the data of the state of the first logic stage of the electronic circuit within the first storage element in a second power gating operation mode.
摘要翻译：公开了一种系统，电子电路和方法。方法实施例包括接收与电子电路的电源门控操作模式相关联的控制信号，基于电源门控操作模式将参考电压施加到电子电路，以及维护表示电子电路的逻辑级状态的数据基于电源门控操作模式。在所描述的实施例中，维护包括在第一电源门控操作模式中将电子电路的第一逻辑级的状态的数据存储在第一存储元件内，以及恢复电子电路的第二逻辑级的状态的数据在第二电源门控操作模式中利用第一存储元件内的电子电路的第一逻辑级的状态的数据。

48. 发明授权

US08533578B2 Error detection in a content addressable memory (CAM) and method of operation 有权
标题翻译：内容可寻址存储器（CAM）中的错误检测和操作方法
公开(公告)号：US08533578B2
公开(公告)日：2013-09-10
申请号：US12813974
申请日：2010-06-11
申请人： Ravindraraj Ramaraju , Ambica Ashok , Kent W. Li
发明人： Ravindraraj Ramaraju , Ambica Ashok , Kent W. Li
IPC分类号： G11C29/00
CPC分类号： G11C15/04 , G06F11/1064 , H03M13/09
摘要： A method for accessing a content addressable memory (CAM) system having a CAM and random access memory (RAM) includes providing comparand data to the CAM, comparing the comparand data to entries of the CAM to determine a matching CAM entry and asserting a match signal corresponding to the matching CAM entry. In response to asserting the match signal, the method further includes providing output data, an output parity bit, and an output complement parity bit from the RAM, using the comparand data to generate a generated parity bit, and providing an error indicator based on the generated parity bit, the output parity bit, and the output complement parity bit. The error indicator may indicate an error when the generated parity bit is not equal to the output parity bit or when the output parity bit is equal to the output complement parity bit.
摘要翻译：一种用于访问具有CAM和随机存取存储器（RAM）的内容可寻址存储器（CAM）系统的方法，包括向CAM提供比较数据，将比较数据与CAM的条目进行比较，以确定匹配的CAM条目并确定匹配信号对应于匹配的CAM条目。响应于确定匹配信号，该方法还包括使用比较数据从RAM提供输出数据，输出奇偶校验位和输出补码奇偶校验位，以产生生成的奇偶校验位，并且基于产生的奇偶校验位，输出奇偶校验位和输出补码奇偶校验位。当产生的奇偶校验位不等于输出奇偶校验位时，或当输出奇偶校验位等于输出补码奇偶校验位时，错误指示器可能指示错误。

49. 发明授权

US08493121B1 Reconfigurable flip-flop 有权
公开(公告)号：US08493121B1
公开(公告)日：2013-07-23
申请号：US13605385
申请日：2012-09-06
申请人： Ravindraraj Ramaraju
发明人： Ravindraraj Ramaraju
IPC分类号： H03K3/356
CPC分类号： H03K3/3568 , H03K3/356156
摘要： A device (300, 1000) provides a dual-edge triggered flip-flop (DETFF) that is reconfigurable to a master-slave flip-flop (MSFF). The device includes a reconfigurable MUX-D flip-flop including two distinct circuit configurations. In a first configuration, two latches or storage elements (340, 360, 1040, 1060) are operating in series to provide a MUX-D flip-flop. In a second configuration, the storage elements (340, 360, 1040, 1060) are operating in parallel to provide a dual-edge triggered flip-flop (DETFF).

50. 发明授权

US08189408B2 Memory device having shifting capability and method thereof 有权
标题翻译：具有移动能力的存储装置及其方法
公开(公告)号：US08189408B2
公开(公告)日：2012-05-29
申请号：US12620314
申请日：2009-11-17
申请人： Ravi Gupta , David R. Bearden , Ravindraraj Ramaraju
发明人： Ravi Gupta , David R. Bearden , Ravindraraj Ramaraju
IPC分类号： G11C7/00
CPC分类号： G11C7/1006 , G11C7/1075 , G11C7/18 , G11C19/00 , G11C19/28
摘要： An array of memory bit cells are operable to provide a memory device having data shifting capability, so that data can be flexibly stored and retrieved from the memory device in both parallel and serial fashions. The memory array can thus be used for conventional memory storage operations, and also for operations, such as matrix operations, that provide for the alteration of the arrangement of stored data elements.
摘要翻译：存储器位单元阵列可操作以提供具有数据移位能力的存储器件，从而能够以并行和串行方式从存储器件灵活地存储和检索数据。因此，存储器阵列可以用于常规存储器存储操作，并且还可以用于提供对存储的数据元素的布置的改变的诸如矩阵操作的操作。

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