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41. 发明申请

US20140110756A1 SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20140110756A1
公开(公告)日：2014-04-24
申请号：US13981808
申请日：2012-07-24
申请人： Huilong Zhu , Qingqing Liang , Huicai Zhong , Hao Wu
发明人： Huilong Zhu , Qingqing Liang , Huicai Zhong , Hao Wu
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/66477 , H01L21/2815 , H01L29/517 , H01L29/66545 , H01L29/66628 , H01L29/66636 , H01L29/66772 , H01L29/7848 , H01L29/78618 , H01L29/78639 , H01L29/78654
摘要： Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, the method comprises: sequentially forming a sacrificial layer and a semiconductor layer on a substrate; forming a first cover layer on the semiconductor layer; forming an opening extending into the substrate with the first cover layer as a mask; selectively removing at least a portion of the sacrificial layer through the opening, and filling an insulating material in a gap due to removal of the sacrificial layer; forming one of source and drain regions in the opening; forming a second cover layer on the substrate; forming the other of the source and drain regions with the second cover layer as a mask; removing a portion of the second cover layer; and forming a gate dielectric layer, and forming a gate conductor in the form of spacer on a sidewall of a remaining portion of the second cover layer.
摘要翻译：公开了半导体装置及其制造方法。在一个实施例中，该方法包括：在衬底上顺序形成牺牲层和半导体层; 在所述半导体层上形成第一覆盖层; 形成以第一覆盖层为掩模延伸到基板的开口; 通过所述开口选择性地去除所述牺牲层的至少一部分，并且由于去除所述牺牲层而在绝缘材料中填充绝缘材料; 在开口中形成源极和漏极区域之一; 在所述基板上形成第二覆盖层; 以第二覆盖层为掩模形成源区和漏区中的另一个; 去除所述第二覆盖层的一部分; 以及形成栅极电介质层，并且在所述第二覆盖层的剩余部分的侧壁上形成隔板形式的栅极导体。

42. 发明授权

US08703558B2 Graphene device and method for manufacturing the same 有权
标题翻译：石墨烯装置及其制造方法
公开(公告)号：US08703558B2
公开(公告)日：2014-04-22
申请号：US13140141
申请日：2011-02-24
申请人： Qingqing Liang , Zhi Jin , Wenwu Wang , Huicai Zhong , Xinyu Liu , Huilong Zhu
发明人： Qingqing Liang , Zhi Jin , Wenwu Wang , Huicai Zhong , Xinyu Liu , Huilong Zhu
IPC分类号： H01L21/00
CPC分类号： H01L29/778 , H01L29/1606 , H01L29/78603 , H01L29/78618 , H01L29/78684
摘要： The invention provides a graphene device structure and a method for manufacturing the same, the device structure comprising a graphene layer; a gate region in contact with the graphene layer; semiconductor doped regions formed in the two opposite sides of the gate region and in contact with the graphene layer, wherein the semiconductor doped regions are isolated from the gate region; a contact formed on the gate region and contacts formed on the semiconductor doped regions. The on-off ratio of the graphene device is increased through the semiconductor doped regions without increasing the band gap of the graphene material, i.e., without affecting the mobility of the material or the speed of the device, thereby increasing the applicability of the graphene material in CMOS devices.
摘要翻译：本发明提供了一种石墨烯器件结构及其制造方法，该器件结构包括石墨烯层; 与石墨烯层接触的栅极区域; 半导体掺杂区域形成在栅极区域的两个相对侧并与石墨烯层接触，其中半导体掺杂区域与栅极区域隔离; 在栅极区域上形成的触点和形成在半导体掺杂区域上的触点。通过半导体掺杂区域增加石墨烯器件的开关比，而不增加石墨烯材料的带隙，即不影响材料的迁移率或器件的速度，从而增加石墨烯材料的适用性在CMOS设备中。

43. 发明授权

US08269307B2 Shallow trench isolation structure and method for forming the same 有权
标题翻译：浅沟隔离结构及其形成方法
公开(公告)号：US08269307B2
公开(公告)日：2012-09-18
申请号：US13119004
申请日：2011-01-27
申请人： Huicai Zhong , Haizhou Yin , Qingqing Liang , Huilong Zhu
发明人： Huicai Zhong , Haizhou Yin , Qingqing Liang , Huilong Zhu
IPC分类号： H01L29/15
CPC分类号： H01L29/7846 , H01L21/76224
摘要： The invention provides a STI structure and a method for manufacturing the same. The STI includes a semiconductor substrate; a first trench formed on the upper surface of the semiconductor substrate and filled with an epitaxial layer, wherein the upper surface of the epitaxial layer is higher than that of the semiconductor substrate; and a second trench formed on the epitaxial layer and filled with a first dielectric layer, wherein the upper surface of the first dielectric layer is flush with that of the epitaxial layer, and the width of the second trench is smaller than that of the first trench. The invention reduces the influences of divots on performance of the semiconductor device.
摘要翻译：本发明提供一种STI结构及其制造方法。 STI包括半导体衬底; 形成在所述半导体衬底的上表面上并填充有外延层的第一沟槽，其中所述外延层的上表面高于所述半导体衬底的所述外表面; 以及形成在所述外延层上并且填充有第一介电层的第二沟槽，其中所述第一电介质层的上表面与所述外延层的上表面齐平，并且所述第二沟槽的宽度小于所述第一沟槽的宽度。本发明减少了对于半导体器件性能的影响。

44. 发明申请

US20120153393A1 Transistor, Semiconductor Device Comprising the Transistor and Method for Manufacturing the Same 有权
标题翻译：晶体管，包括晶体管的半导体器件及其制造方法
公开(公告)号：US20120153393A1
公开(公告)日：2012-06-21
申请号：US13144906
申请日：2011-02-25
申请人： Qingqing Liang , Huilong Zhu , Huicai Zhong
发明人： Qingqing Liang , Huilong Zhu , Huicai Zhong
IPC分类号： H01L29/772 , H01L21/8238 , H01L21/336
CPC分类号： H01L29/78648 , H01L21/8213 , H01L21/8252 , H01L21/84 , H01L27/0605 , H01L27/1203 , H01L29/66545 , H01L29/66628
摘要： The invention relates to a transistor, a semiconductor device comprising the transistor and manufacturing methods for the transistor and the semiconductor device. The transistor according to the invention comprises: a substrate comprising at least a base layer, a first semiconductor layer, an insulating layer and a second semiconductor layer stacked sequentially; a gate stack formed on the second semiconductor layer; a source region and a drain region located on both sides of the gate stack respectively; a back gate comprising a back gate dielectric and a back gate electrode formed by the insulating layer and the first semiconductor layer, respectively; and a back gate contact formed on a portion of the back gate electrode. The back gate contact comprises an epitaxial part raised from the surface of the back gate electrode, and each of the source region and the drain region comprises an epitaxial part raised from the surface of the second semiconductor layer. As compared to a conventional transistor, the manufacturing process of the transistor of the invention is simplified and the cost of manufacture is reduced.
摘要翻译：本发明涉及晶体管，包括晶体管的半导体器件和用于晶体管和半导体器件的制造方法。根据本发明的晶体管包括：至少包括基层，第一半导体层，绝缘层和顺序层叠的第二半导体层的基板; 形成在所述第二半导体层上的栅叠层; 分别位于栅极堆叠的两侧的源极区域和漏极区域; 包括分别由所述绝缘层和所述第一半导体层形成的背栅电介质和背栅电极的背栅; 以及形成在背栅电极的一部分上的背栅极接触。背栅极触点包括从背栅电极的表面凸起的外延部分，源区和漏区中的每一个包括从第二半导体层的表面凸出的外延部。与常规晶体管相比，本发明的晶体管的制造工艺简化，制造成本降低。

45. 发明授权

US08779514B2 Transistor and method for manufacturing the same 有权
标题翻译：晶体管及其制造方法
公开(公告)号：US08779514B2
公开(公告)日：2014-07-15
申请号：US13144903
申请日：2011-02-25
申请人： Qingqing Liang , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Huicai Zhong , Huilong Zhu
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/78648 , H01L29/66545 , H01L29/66628
摘要： The invention relates to a transistor and a method for manufacturing the transistor. The transistor according to an embodiment of the invention may comprise: a substrate which comprises at least a back gate of the transistor, an insulating layer and a semiconductor layer stacked sequentially, wherein the back gate of the transistor is used for adjusting the threshold voltage of the transistor; a gate stack formed on the semiconductor layer, wherein the gate stack comprises a gate dielectric and a gate electrode formed on the gate dielectric; a spacer formed on sidewalls of the gate stack; and a source region and a drain region located on both sides of the gate stack, respectively, wherein the height of the gate stack is lower than the height of the spacer. The transistor enables the height of the gate stack to be reduced and therefore the performance of the transistor is improved.
摘要翻译：本发明涉及晶体管及其制造方法。根据本发明的实施例的晶体管可以包括：至少包括晶体管的背栅极，绝缘层和顺序层叠的半导体层的衬底，其中晶体管的背栅极用于调节晶体管的阈值电压晶体管; 形成在所述半导体层上的栅极堆叠，其中所述栅极堆叠包括形成在所述栅极电介质上的栅极电介质和栅电极; 形成在栅叠层的侧壁上的间隔物; 以及分别位于栅极堆叠的两侧的源极区域和漏极区域，其中栅极叠层的高度低于间隔物的高度。该晶体管能够降低栅极叠层的高度，从而提高晶体管的性能。

46. 发明授权

US08592911B2 Asymmetric semiconductor device having a high-k/metal gate and method of manufacturing the same 有权
标题翻译：具有高k /金属栅极的非对称半导体器件及其制造方法
公开(公告)号：US08592911B2
公开(公告)日：2013-11-26
申请号：US13063717
申请日：2010-09-25
申请人： Qingqing Liang , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Huicai Zhong , Huilong Zhu
IPC分类号： H01L29/78
CPC分类号： H01L29/4983 , H01L21/28105 , H01L21/2815 , H01L21/823462 , H01L21/823468 , H01L29/495 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66659
摘要： A semiconductor device and a method of manufacturing the same are provided. The semiconductor device has a metal sidewall spacer on the sidewall of a gate electrode on the drain region side. The metal sidewall spacer is made of such metals as Ta, which has an oxygen scavenging effect and can effectively reduce EOT on the drain region side, and thus the ability to control the short channel is effectively increased. In addition, since EOT on the source region side is larger, the carrier mobility of the device will not be degraded. Moreover, such asymmetric device may have a better driving performance.
摘要翻译：提供半导体器件及其制造方法。半导体器件在漏极区侧的栅电极的侧壁上具有金属侧壁间隔物。金属侧壁间隔物由具有除氧效果的Ta等金属制成，能够有效地减少漏区侧面的EOT，有效地提高控制短路的能力。此外，由于源区域侧的EOT较大，所以器件的载流子迁移率不会降低。此外，这种不对称装置可能具有更好的驱动性能。

47. 发明授权

US08557677B2 Stack-type semiconductor device and method for manufacturing the same 有权
标题翻译：叠层型半导体器件及其制造方法
公开(公告)号：US08557677B2
公开(公告)日：2013-10-15
申请号：US13120792
申请日：2011-02-17
申请人： Qingqing Liang , Huicai Zhong , Chao Zhao , Huilong Zhu
发明人： Qingqing Liang , Huicai Zhong , Chao Zhao , Huilong Zhu
IPC分类号： H01L21/30
CPC分类号： H01L25/50 , H01L21/6835 , H01L23/481 , H01L25/0657 , H01L2221/68327 , H01L2221/68359 , H01L2221/68363 , H01L2221/68368 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A stack-type semiconductor device includes a semiconductor substrate; and a plurality of wafer assemblies arranged in various levels on the semiconductor substrate, in which the wafer assembly in each level includes an active part and an interconnect part, and the active part and the interconnect part each have conductive through vias, wherein the conductive through vias in the active part are aligned with the conductive through vias in the interconnect part in a vertical direction, so that the active part in each level is electrically coupled with the active part in the previous level and/or the active part in the next level by the conductive through vias. Such a stack-type semiconductor device and the related methods can be applied in a process after the FEOL or in a semiconductor chip packaging process and provide a 3-dimensional semiconductor device of high integration and high reliability.
摘要翻译：堆叠型半导体器件包括半导体衬底; 以及在所述半导体衬底上以各种级别布置的多个晶片组件，其中每个级中的所述晶片组件包括有源部分和互连部分，并且所述有源部分和所述互连部件各自具有导电通孔，其中所述导电通孔有源部分中的通孔在垂直方向上与互连部分中的导电通孔对准，使得每个电平中的有源部分与先前电平中的有源部分和/或下一级的有源部分电耦合通过导电通孔。这种叠层型半导体器件及相关方法可以在FEOL之后的工艺中或半导体芯片封装工艺中应用，并提供高集成度和高可靠性的三维半导体器件。

48. 发明申请

US20130140624A1 Semiconductor Structure and Method for Forming The Semiconductor Structure 有权
标题翻译：用于形成半导体结构的半导体结构和方法
公开(公告)号：US20130140624A1
公开(公告)日：2013-06-06
申请号：US13807010
申请日：2011-11-30
申请人： Qingqing Liang , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Huicai Zhong , Huilong Zhu
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7827 , H01L21/28008 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/115 , H01L27/11556 , H01L27/1203 , H01L29/458 , H01L29/4908 , H01L29/66666 , H01L29/78642
摘要： The invention discloses a semiconductor structure comprising: a substrate, a conductor layer, and a dielectric layer surrounding the conductor layer on the substrate; a first insulating layer covering both of the conductor layer and the dielectric layer; a gate conductor layer formed on the first insulating layer, and a dielectric layer surrounding the gate conductor layer; and a second insulating layer covering both of the gate conductor layer and the dielectric layer surrounding the gate conductor layer; wherein a through hole filled with a semiconductor material penetrates through the gate conductor layer perpendicularly, the bottom of the through hole stops on the conductor layer, and a first conductor plug serving as a drain/source electrode is provided on the top of the through hole; and a second conductor plug serving as a source/drain electrode electrically contacts the conductor layer, and a third conductor plug serving as a gate electrode electrically contacts the gate conductor layer.
摘要翻译：本发明公开了一种半导体结构，包括：衬底，导体层和围绕衬底上的导体层的电介质层; 覆盖所述导体层和所述电介质层的第一绝缘层; 形成在第一绝缘层上的栅极导体层和围绕栅极导体层的电介质层; 以及覆盖所述栅极导体层和围绕所述栅极导体层的所述电介质层的第二绝缘层; 其中填充有半导体材料的通孔垂直地穿过栅极导体层，通孔的底部停在导体层上，并且用作漏极/源极的第一导体插塞设置在通孔的顶部 ; 和用作源/漏电极的第二导体插头与导体层电接触，并且用作栅电极的第三导体插头电接触栅极导体层。

49. 发明授权

US08410609B2 Semiconductor device having carbon nanotube interconnects contact deposited with different orientation and method for manufacturing the same 有权
标题翻译：具有不同取向沉积的碳纳米管互连的半导体器件及其制造方法
公开(公告)号：US08410609B2
公开(公告)日：2013-04-02
申请号：US13129321
申请日：2011-02-26
申请人： Huicai Zhong , Qingqing Liang , Zhijiong Luo , Huilong Zhu
发明人： Huicai Zhong , Qingqing Liang , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L29/40 , H01L21/00
CPC分类号： H01L23/53276 , H01L21/76807 , H01L21/76843 , H01L21/76846 , H01L21/76847 , H01L21/76877 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a semiconductor device structure and a method for manufacturing the same; the structure comprises: a semiconductor substrate on which a device structure is formed thereon; an interlayer dielectric layer formed on the device structure, wherein a trench is formed in the interlayer dielectric layer, the trench comprises an incorporated via trench and a conductive wiring trench, and the conductive wiring trench is positioned on the via trench; and a conductive layer filled in the trench, wherein the conductive layer is electrically connected with the device structure; wherein the conductive layer comprises a conductive material and a nanotube/wire layer surrounded by the conductive material. Wherein, the conductive layer comprises a conductive material and a nanotube/wire layer surrounded by the conductive material. The conductive layer of the structure has better thermal conductivity, conductivity and high anti-electromigration capability, thus is able to effectively prevent metal ions from diffusing outwards.
摘要翻译：半导体器件结构及其制造方法技术领域本发明涉及半导体器件结构及其制造方法。该结构包括：其上形成有器件结构的半导体衬底; 在所述器件结构上形成的层间电介质层，其中在所述层间介质层中形成沟槽，所述沟槽包括并入的通孔沟槽和导电布线沟槽，并且所述导电布线沟槽位于所述通孔沟槽上; 以及填充在所述沟槽中的导电层，其中所述导电层与所述器件结构电连接; 其中所述导电层包括由所述导电材料包围的导电材料和纳米管/线层。其中，导电层包括由导电材料包围的导电材料和纳米管/线层。该结构的导电层具有较好的导热性，导电性和较高的抗电迁移能力，能有效防止金属离子向外扩散。

50. 发明申请

US20130015526A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130015526A1
公开(公告)日：2013-01-17
申请号：US13380806
申请日：2011-08-09
申请人： Qingqing Liang , Huilong Zhu , Huicai Zhong
发明人： Qingqing Liang , Huilong Zhu , Huicai Zhong
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/7849 , H01L21/823807 , H01L21/84 , H01L27/1203
摘要： The invention relates to a semiconductor device and a method for manufacturing such a semiconductor device. A semiconductor device according to an embodiment of the invention comprises: a substrate which comprises a base layer, an insulating layer on the base layer, and a semiconductor layer on the insulating layer; and a first transistor and a second transistor formed on the substrate, the first and second transistors being isolated from each other by a trench isolation structure formed in the substrate. Wherein at least a part of the base layer under at least one of the first and second transistors is strained, and the strained part of the base layer is adjacent to the insulating layer. The semiconductor device according to the invention increases the speed of the device and thus improves the performance of the device.
摘要翻译：本发明涉及半导体器件及其制造方法。根据本发明实施例的半导体器件包括：基底，其包括基底层，基底层上的绝缘层和绝缘层上的半导体层; 以及形成在所述衬底上的第一晶体管和第二晶体管，所述第一晶体管和所述第二晶体管通过形成在所述衬底中的沟槽隔离结构彼此隔离。其中在第一和第二晶体管中的至少一个晶体管下方的基底层的至少一部分被应变，并且基底层的应变部分与绝缘层相邻。根据本发明的半导体器件增加了器件的速度，从而提高了器件的性能。

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