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41. 发明申请

US20110141832A1 PROGRAM CYCLE SKIP 有权
标题翻译：程序循环跳
公开(公告)号：US20110141832A1
公开(公告)日：2011-06-16
申请号：US12638729
申请日：2009-12-15
申请人： Gopinath Balakrishnan , Luca Fasoli , Tz-Yi Liu , Yuheng Zhang , Yan Li
发明人： Gopinath Balakrishnan , Luca Fasoli , Tz-Yi Liu , Yuheng Zhang , Yan Li
IPC分类号： G11C11/416 , G11C7/10
CPC分类号： G11C13/0069 , G11C5/02 , G11C13/0007 , G11C13/0061 , G11C17/165 , G11C17/18 , G11C2013/0076 , G11C2013/0085 , G11C2213/71
摘要： A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.
摘要翻译：非易失性存储系统包括在编程页面（或其他单元）数据时跳过编程周期的技术。在对页面（或其他单元）数据的当前子集进行编程时，系统将评估页面（或其他单元）的下一个子集是否应编程为非易失性存储元素或跳过。不应被跳过的页面（或其他单元）的子集被编程到非易失性存储元件中。一些实施例包括将适当数据传送到临时锁存器/寄存器，以准备编程，同时评估是编程还是跳过编程。

42. 发明申请

US20110141819A1 SEGMENTED BITSCAN FOR VERIFICATION OF PROGRAMMING 有权
标题翻译： SEGMENTED BITSCAN用于验证编程
公开(公告)号：US20110141819A1
公开(公告)日：2011-06-16
申请号：US13035539
申请日：2011-02-25
申请人： Yan Li , Teruhiko Kamei , Jeffrey W. Lutze
发明人： Yan Li , Teruhiko Kamei , Jeffrey W. Lutze
IPC分类号： G11C16/10
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/3454 , G11C2211/5621
摘要： A set non-volatile storage elements are subjected to a programming process in order to store a set of data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target condition to store the appropriate data. Decisions about whether to continue programming or whether the programming is successful are made based on whether overlapping groups of the non-volatile storage elements have less than a threshold number of non-volatile storage elements that are not properly programmed.
摘要翻译：一组非易失性存储元件经受编程处理以便存储一组数据。在编程过程中，执行一个或多个验证操作以确定非易失性存储元件是否已经达到其目标条件以存储适当的数据。关于是继续编程还是编程成功的决定是基于非易失性存储元件的重叠组是否具有小于非正确编程的非易失性存储元件的阈值数量来进行。

43. 发明申请

US20110141818A1 Nonvolatile Memory and Method for Compensating During Programming for Perturbing Charges of Neighboring Cells 有权
标题翻译：非易失性存储器和在相邻单元的扰动充电编程期间补偿的方法
公开(公告)号：US20110141818A1
公开(公告)日：2011-06-16
申请号：US13029787
申请日：2011-02-17
申请人： Yan Li
发明人： Yan Li
IPC分类号： G11C16/06
CPC分类号： G11C8/10 , G11C16/3418 , G11C16/3445 , G11C16/3454
摘要： Shifts in the apparent charge stored on a charge storing element of a non-volatile memory cell can occur because of the coupling of an electric field based on the charge stored in adjacent charge storing elements. To compensate for this coupling, the programming process for a given memory cell can take into account the target programmed state of one or more adjacent memory cell. The amount of programming is verified after each programming pulse and the standard verify level for the programming cell is dependent on the target state. The verify level is further offset lower dependent on the amount of perturbation from neighboring cells, determinable by their target states. The verify level is preferably virtually offset by biasing adjacent word lines instead of actually offsetting the standard verify level. For soft-programming erased cells, neighboring cells on both adjacent word lines are taken into account.
摘要翻译：由于存储在相邻的电荷存储元件中的电荷的电场的耦合，可能会发生存储在非易失性存储单元的电荷存储元件上的视在电荷的变化。为了补偿该耦合，给定存储器单元的编程过程可以考虑一个或多个相邻存储器单元的目标编程状态。在每个编程脉冲之后验证编程量，编程单元的标准验证电平取决于目标状态。验证级别进一步偏移较低，取决于相邻小区的扰动量，可由其目标状态确定。验证级别优选地通过偏置相邻字线而不是实际上抵消标准验证电平而被虚拟地偏移。对于软编程擦除的单元，考虑两个相邻字线上的相邻单元。

44. 发明授权

US07961706B2 Control method, system and function entity for reporting bearer event of signaling IP flow 有权
标题翻译：控制方法，系统和功能实体，用于报告信令IP流的承载事件
公开(公告)号：US07961706B2
公开(公告)日：2011-06-14
申请号：US12634147
申请日：2009-12-09
申请人： Shibi Huang , Peng Zhao , Yuxin Mao , Shiyong Tan , Weihua Wei , Yan Li
发明人： Shibi Huang , Peng Zhao , Yuxin Mao , Shiyong Tan , Weihua Wei , Yan Li
IPC分类号： H04J3/24
CPC分类号： H04W4/20 , H04L12/14 , H04L12/1428 , H04L12/1457 , H04L12/56 , H04L65/1016 , H04L65/80
摘要： A control method, system and function entity for reporting a bearer event of a signaling IP flow are provided. Flow identifier information such as a 5-tuple is generated for a signaling IP flow and a media IP flow so as to unify a mechanism for reporting a signaling path status and a mechanism for reporting a bearer event of a media IP flow, so that the mechanism for reporting a signaling path status is not limited by the parameter of Flow Usage, the PDP context with a signaling tag, thereby establishing corresponding PCC rules for signaling and the association between a signaling IP flow and a bearer. A method for reporting a signaling path status is further provided in the invention. In the method, for a default PDP context or a PDP context of a signaling IP flow, the predefined PCC rules are activated or signaling PCC rules generated in accordance with an Application Function address are installed, thereby an IP signaling path status is reported in accordance with rule names of the predefine PCC rules or the signaling PCC rules.
摘要翻译：提供了用于报告信令IP流的承载事件的控制方法，系统和功能实体。为信令IP流和媒体IP流生成诸如5元组的流标识符信息，以便统一用于报告信令路径状态的机制和用于报告媒体IP流的承载事件的机制，使得用于报告信令路径状态的机制不受Flow Usage的参数，具有信令标签的PDP上下文的限制，从而建立用于信令的相应PCC规则以及信令IP流和承载之间的关联。本发明还提供了一种报告信令路径状态的方法。在该方法中，对于默认PDP上下文或信令IP流的PDP上下文，激活预定PCC规则或者安装根据应用功能地址生成的信令PCC规则，从而根据报告IP信令路径状态具有预定义PCC规则或信令PCC规则的规则名称。

45. 发明申请

US20110122702A1 PROGRAMMING MEMORY WITH SENSING-BASED BIT LINE COMPENSATION TO REDUCE CHANNEL-TO-FLOATING GATE COUPLING 有权
标题翻译：具有基于感测的位线补偿的编程存储器可减少通道至浮动门的耦合
公开(公告)号：US20110122702A1
公开(公告)日：2011-05-26
申请号：US12624595
申请日：2009-11-24
申请人： Yan Li
发明人： Yan Li
IPC分类号： G11C16/10 , G11C16/04 , G11C16/26
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/10 , G11C16/3418 , G11C16/3427
摘要： During programming of storage elements, channel-to-floating gate coupling effects are compensated to avoid increased programming speed and threshold voltage distribution widening. In connection with a programming iteration, unselected bit lines voltages are stepped up to induce coupling to selected bit lines, and the amount of coupling which is experienced by the selected bit lines is sensed. When a program pulse is applied, voltages of the selected bit lines are set based on the amount of coupling. The bit line voltage is set higher when more coupling is sensed. The amount of coupling experience by a given selected bit line is a function of its proximity to unselected bit lines. One or more coupling thresholds can be used to indicate that a given selected bit line has one or two adjacent unselected bit lines, respectively.
摘要翻译：在存储元件的编程期间，补偿了沟道到浮置栅极耦合效应，以避免增加的编程速度和阈值电压分布加宽。结合编程迭代，非选择的位线电压被升高以感应到选定位线的耦合，并且感测所选位线所经历的耦合量。当施加编程脉冲时，基于耦合量设置所选位线的电压。当检测到更多的耦合时，位线电压被设置得更高。给定选定位线的耦合体验量是其与未选定位线的接近度的函数。可以使用一个或多个耦合阈值来指示给定的所选位线分别具有一个或两个相邻的未选位线。

46. 发明申请

US20110122695A1 PROGRAMMING MEMORY WITH BIT LINE FLOATING TO REDUCE CHANNEL-TO-FLOATING GATE COUPLING 失效
标题翻译：具有位线浮动的编程存储器可减少通道至浮动门的耦合
公开(公告)号：US20110122695A1
公开(公告)日：2011-05-26
申请号：US12624584
申请日：2009-11-24
申请人： Yan Li , Anubhav Khandelwal
发明人： Yan Li , Anubhav Khandelwal
IPC分类号： G11C16/10 , G11C16/24 , G11C16/04
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/10 , G11C16/3418 , G11C16/3427
摘要： During programming of storage elements, channel-to-floating gate coupling effects are compensated to avoid increased programming speed and threshold voltage distribution widening. Programming speed can be adjusted by grounding the bit line of a selected storage element until it reaches a verify level which is below a target verify level of its target data state, after which the bit line is floated so that programming speed is slowed. The verify level which triggers the floating can be a target verify level of a data state that is one or more states below the target data state. Or, the verify level which triggers the floating can be an offset verify level of the target data state. An option is to raise the bit line voltage before it floats, to enter a slow programming mode, in which case there is a double slow down.
摘要翻译：在存储元件的编程期间，补偿了沟道到浮置栅极耦合效应，以避免增加的编程速度和阈值电压分布加宽。编程速度可以通过将选定的存储元件的位线接地直到其达到低于其目标数据状态的目标验证电平的验证电平来调整，此后位线被浮置，使得编程速度变慢。触发浮动的验证级别可以是低于目标数据状态的一个或多个状态的数据状态的目标验证级别。或者，触发浮动的验证级别可以是目标数据状态的偏移验证级别。一个选项是在浮点运算之前提高位线电压，进入缓慢的编程模式，在这种情况下会出现双倍的减速。

47. 发明授权

US07894273B2 Nonvolatile memory and method with reduced program verify by ignoring fastest and/or slowest programming bits 有权
标题翻译：通过忽略最快和/或最慢的编程位来减少程序验证的非易失性存储器和方法
公开(公告)号：US07894273B2
公开(公告)日：2011-02-22
申请号：US12407665
申请日：2009-03-19
申请人： Yan Li , Yupin Kawing Fong , Siu Lung Chan
发明人： Yan Li , Yupin Kawing Fong , Siu Lung Chan
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C11/5628 , G11C16/0483 , G11C2211/5621
摘要： A group of non-volatile memory cells are programmed in a programming pass by a series of incremental programming pulses where each pulse is followed by a program-verify and possibly program-inhibition step. Performance is improved during the programming pass by delayed starting and prematurely terminating the various verify levels that demarcate the multiple memory states. This amounts to skipping the verifying and inhibiting steps of the fastest and slowest programming (fringe) cells of the group. A reference pulse is established when the fastest cells have all been program-verified relative to a first verify level. The starting of what verify level at what pulse will then be delayed relative to the reference pulse. Verifying stops for a given verify level when only a predetermined number of cells remain unverified relative to that given level. Any errors arising from over- or under-programming of the fringe cells are corrected by an error correction code.
摘要翻译：一组非易失性存储器单元通过一系列递增编程脉冲在编程过程中被编程，其中每个脉冲之后是程序验证和可能的编程禁止步骤。在编程过程中，通过延迟启动和过早终止划分多个存储器状态的各种验证电平来提高性能。这相当于跳过组中最快和最慢编程（边缘）单元的验证和禁止步骤。当最快的单元格相对于第一验证电平全部被程序验证时，建立参考脉冲。什么脉冲上的什么验证电平的开始将相对于参考脉冲被延迟。当相对于该给定级别只有预定数量的单元格未被验证时，验证给定验证级别的停止。由边缘单元的过度编程或编程不足引起的任何错误都由纠错码进行校正。

48. 发明申请

US20110019596A1 METHOD AND APPARATUS FOR MANAGING FLEXIBLE USAGE OF UNPAIRED FREQUENCIES 有权
标题翻译：管理灵活使用不需要的频率的方法和装置
公开(公告)号：US20110019596A1
公开(公告)日：2011-01-27
申请号：US12843467
申请日：2010-07-26
申请人： Yan Li , Lu Gao
发明人： Yan Li , Lu Gao
IPC分类号： H04J1/00
CPC分类号： H04W72/08 , H04W72/0453
摘要： A method, an apparatus, and a computer program product for wireless communication are provided in which it is determined, by a first device, if a transmission using a second frequency band to a second device will result in a parameter exceeding a threshold value, and content is either transmitted using a first frequency band upon a determination that the transmission to the second device will result in the parameter exceeding the threshold, or transmitted using the first frequency band and a second frequency band upon a determination that the transmission to the second device will result in the parameter not exceeding the threshold, wherein the first and second frequency bands are different.
摘要翻译：提供了一种用于无线通信的方法，装置和计算机程序产品，其中由第一设备确定使用第二频带到第二设备的传输是否将导致超过阈值的参数，以及在确定到第二设备的传输将导致参数超过阈值或者在确定到第二设备的传输的情况下使用第一频带和第二频带发送的情况下，使用第一频带来发送内容将导致参数不超过阈值，其中第一和第二频带不同。

49. 发明申请

US20110002169A1 Bad Column Management with Bit Information in Non-Volatile Memory Systems 审中-公开
标题翻译：在非易失性存储器系统中具有位信息的错误列管理
公开(公告)号：US20110002169A1
公开(公告)日：2011-01-06
申请号：US12498220
申请日：2009-07-06
申请人： Yan Li , Kwang-ho Kim , Frank W. Tsai , Aldo Bottelli
发明人： Yan Li , Kwang-ho Kim , Frank W. Tsai , Aldo Bottelli
IPC分类号： G11C16/06 , G11C29/00 , G11C7/10 , G11C16/04
CPC分类号： G11C29/00 , G11C16/10 , G11C29/808
摘要： Column based defect management techniques are presented. Each column of the memory has an associated isolation latch or register whose value indicates whether the column is defective, but in addition to this information, for columns marked as defective, additional information is used to indicate whether the column as a whole is to be treated as defective, or whether just individual bits of the column are defective. The defective elements can then be re-mapped to a redundant element at either the appropriate bit or column level based on the data. When a column is bad, but only on the bit level, the good bits can still be used for data, although this may be done at a penalty of under programming for some bits, as is described further below. A self contained Built In Self Test (BIST) flow constructed to collect the bit information through a set of column tests is also described. Based on this information, the bad bits can be extracted and re-grouped into bytes by the controller or on the memory to more efficiently use the column redundancy area.
摘要翻译：介绍了基于列的缺陷管理技术。存储器的每一列都有一个相关联的隔离锁存器或寄存器，其值表示列是否有缺陷，但是除了该信息之外，对于标记为有缺陷的列，还使用附加信息来指示是否要对列进行整体处理作为缺陷，或者列的单个位是否有缺陷。然后，可以基于该数据将有缺陷的元素重新映射到适当位或列级的冗余元件。当列是坏的但是仅在位电平时，好的位仍然可以用于数据，尽管这可以在对于某些位的编程的惩罚下完成，如下面进一步描述的。还描述了通过一组列测试来构建的用于收集位信息的自建内置自检（BIST）流程。基于该信息，可以通过控制器或存储器提取坏位并将其重新分组为字节，以更有效地使用列冗余区域。

50. 发明授权

US07855992B2 Multi-antenna solution for mobile handset 有权
标题翻译：移动手机的多天线解决方案
公开(公告)号：US07855992B2
公开(公告)日：2010-12-21
申请号：US10540791
申请日：2003-12-22
申请人： Luzhou Xu , Yanzhong Dai , Jian Liu , Ronghui Wu , Min Shi , Yun Yuan , Yan Li
发明人： Luzhou Xu , Yanzhong Dai , Jian Liu , Ronghui Wu , Min Shi , Yun Yuan , Yan Li
IPC分类号： H04W4/00
CPC分类号： H04B7/0897 , H04B7/022 , H04B7/0613 , H04B7/084 , H04B7/0854
摘要： A mobile terminal with multi-antenna (200) based on CDMA, comprises a plurality of groups of radio frequency signal processing modules (202), for transforming received multi-channel radio frequency signals based on CDMA to multi-channel baseband signals; a multi-antenna module (206), for combining said multi-channel baseband signals output from the plurality of groups of radio frequency signal processing modules into single-channel baseband signals according to control information received one-off when said multi-antenna module enables a multi-antenna baseband processing; and a baseband processing module (203), for providing said control information to said multi-antenna module and baseband processing said single-channel baseband signals outputted from said multi-antenna module.
摘要翻译：一种基于CDMA的具有多天线（200）的移动终端包括多组射频信号处理模块（202），用于将接收到的基于CDMA的多频道射频信号变换为多信道基带信号; 多天线模块（206），用于当所述多天线模块使能时，将根据多次接收的控制信息将从多组射频信号处理模块输出的所述多通道基带信号组合为单通道基带信号多天线基带处理; 以及基带处理模块（203），用于向所述多天线模块提供所述控制信息，以及对从所述多天线模块输出的所述单信道基带信号进行基带处理。

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