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41. 发明申请

US20080037343A1 MEMORY HAVING SENSE TIME OF VARIABLE DURATION 有权
标题翻译：具有可变持续时间的记忆
公开(公告)号：US20080037343A1
公开(公告)日：2008-02-14
申请号：US11464124
申请日：2006-08-11
申请人： William C. Moyer , Perry H. Pelley
发明人： William C. Moyer , Perry H. Pelley
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C7/22 , G11C8/08 , G11C8/10 , G11C11/413 , G11C2207/2281
摘要： In one form a memory and method thereof has a memory array having a plurality of memory cells. A bit line precharge operation is based on a clock edge of an external clock signal. A word line is selected after the beginning of the precharge operation. A sense operation is begun after enabling the word line, where the sense operation is for sensing a logic state of a memory cell. A data bit is output from the memory array corresponding to the sensed logic state of the memory cell. In one form the bit line precharge operation further comprises the bit line precharge operation having a predetermined duration that is independent of the clock signal, and the sense operation begins a predetermined delay time after enabling the word line, the sense operation having a variable duration.
摘要翻译：在一种形式中，其存储器及其方法具有具有多个存储单元的存储器阵列。位线预充电操作基于外部时钟信号的时钟边沿。在预充电操作开始之后选择字线。在启用字线之后开始感测操作，其中感测操作用于感测存储器单元的逻辑状态。从与存储单元的检测到的逻辑状态对应的存储器阵列输出数据位。在一种形式中，位线预充电操作还包括具有与时钟信号无关的预定持续时间的位线预充电操作，并且感测操作在使能字线之后开始预定的延迟时间，感测操作具有可变持续时间。

42. 发明授权

US07285976B2 Integrated circuit with programmable-impedance output buffer and method therefor 有权
标题翻译：具有可编程阻抗输出缓冲器的集成电路及其方法
公开(公告)号：US07285976B2
公开(公告)日：2007-10-23
申请号：US11047161
申请日：2005-01-31
申请人： Perry H. Pelley
发明人： Perry H. Pelley
IPC分类号： H03K17/16
CPC分类号： H03K19/0005
摘要： An impedance matching between two integrated circuits is achieved using an impedance measuring circuit in the integrated circuit that contains an impedance-programmable output buffer (IPOB) that is to have its output impedance changed. The impedance measuring device is directly connected to the output of the IPOB so that it is detecting the same impedance that the IPOB will drive and thereby avoids the errors of measuring the resistance of a device that imperfectly models the actual impedance. The impedance measuring device is preferably an analog to digital (A/D) converter that provides a digital output relative to the voltage present on the same terminal as the output of the IPOB. By having the A/D converter on the same integrated circuit as the IPOB, communications difficulties between the A/D converter and the IPOB are minimal.
摘要翻译：使用集成电路中的阻抗测量电路来实现两个集成电路之间的阻抗匹配，该阻抗测量电路包含阻抗可编程输出缓冲器（IPOB），其具有其输出阻抗改变。阻抗测量装置直接连接到IPOB的输出端，以便它检测到IPOB将驱动的阻抗相同，从而避免测量不实际模拟实际阻抗的器件的电阻误差。阻抗测量装置优选地是模数（A / D）转换器，其提供相对于与IPOB的输出相同的终端上存在的电压的数字输出。通过使A / D转换器与IPOB相同的集成电路，A / D转换器和IPOB之间的通信困难很小。

43. 发明授权

US07221613B2 Memory with serial input/output terminals for address and data and method therefor 有权
标题翻译：具有用于地址和数据的串行输入/输出端子的存储器及其方法
公开(公告)号：US07221613B2
公开(公告)日：2007-05-22
申请号：US10854554
申请日：2004-05-26
申请人： Perry H. Pelley , Carlos A. Greaves
发明人： Perry H. Pelley , Carlos A. Greaves
IPC分类号： G11C8/00
CPC分类号： G11C11/40618 , G11C11/406 , G11C11/40615
摘要： A memory (10) has a plurality of memory cells, a transceiver (56) for receiving a low voltage high frequency differential address signal, and a serial input/output data port (52, 54) for receiving a high frequency low voltage differential data signal. The memory (10) can operate in one of two different modes, a normal mode and a cache line mode. In cache line mode, the memory can access an entire cache line from a single address. A fully hidden refresh mode allows for timely refresh operations while operating in cache line mode. Data is scored in the memory array (14) by interleaving in multiple sub-arrays (15, 17). During a hidden refresh mode of operation, one sub-array (15) is accessed while another sub-array (17) is refreshed. Two or more of the memories (10) may be chained together to provide a high speed low power memory system.
摘要翻译：存储器（10）具有多个存储单元，用于接收低电压高频差分地址信号的收发器（56）和用于接收高频低电压差分数据的串行输入/输出数据端口（52,54）信号。存储器（10）可以以两种不同模式之一工作，即正常模式和高速缓存行模式。在高速缓存行模式下，内存可以从单个地址访问整个高速缓存行。完全隐藏的刷新模式允许在高速缓存线模式下运行时进行及时的刷新操作。通过在多个子阵列（15,17）中进行交织，在存储器阵列（14）中记录数据。在隐藏的刷新操作模式期间，一个子阵列（15）被访问，而另一个子阵列（17）被刷新。两个或多个存储器（10）可以链接在一起以提供高速低功率存储器系统。

44. 发明授权

US06781908B1 Memory having variable refresh control and method therefor 有权
标题翻译：具有可变刷新控制的存储器及其方法
公开(公告)号：US06781908B1
公开(公告)日：2004-08-24
申请号：US10370011
申请日：2003-02-19
申请人： Perry H. Pelley , John M. Burgan
发明人： Perry H. Pelley , John M. Burgan
IPC分类号： G11C700
CPC分类号： G11C29/028 , G11C7/1045 , G11C8/18 , G11C11/401 , G11C11/406 , G11C11/40615 , G11C11/40626 , G11C29/006 , G11C29/02 , G11C29/50016 , G11C2211/4061
摘要： A memory (10) has a memory array (12), a charge pump (18), a voltage regulator (20), a refresh control circuit (16), and a refresh counter (22). The charge pump (18) provides a substrate bias to the memory array (12). The voltage regulator (20) provides a pump enable signal for maintaining a voltage level of the substrate bias within upper and lower limits. The refresh control circuit (16) controls refresh operations. The refresh counter (22) is coupled to receive the pump enable signal, and in response, provides a refresh timing signal to the refresh control circuit (16) to control a refresh rate of the memory array (12). A programmable fuse circuit (26) is provided to program the refresh rate using the counter (22). The programmable fuse circuit (26) may be programmed during wafer probe testing or board level burn-in. A built-in self test (BIST) circuit (24) may be included to facilitate testing.
摘要翻译：存储器（10）具有存储器阵列（12），电荷泵（18），电压调节器（20），刷新控制电路（16）和刷新计数器（22）。电荷泵（18）向存储器阵列（12）提供衬底偏置。电压调节器（20）提供泵使能信号，用于将衬底偏置的电压电平维持在上限和下限内。刷新控制电路（16）控制刷新操作。刷新计数器（22）被耦合以接收泵使能信号，并且作为响应，向刷新控制电路（16）提供刷新定时信号以控制存储器阵列（12）的刷新率。提供可编程熔丝电路（26）以使用计数器（22）对刷新率进行编程。可编程熔丝电路（26）可以在晶圆探针测试或板级老化期间进行编程。可以包括内置的自检（BIST）电路（24）以便于测试。

45. 发明授权

US09318451B2 Wirebond recess for stacked die 有权
标题翻译：用于堆叠模具的导线键槽
公开(公告)号：US09318451B2
公开(公告)日：2016-04-19
申请号：US14068637
申请日：2013-10-31
申请人： Tim V. Pham , Michael B. McShane , Perry H. Pelley , Tab A. Stephens
发明人： Tim V. Pham , Michael B. McShane , Perry H. Pelley , Tab A. Stephens
IPC分类号： H01L23/48 , H01L23/52 , H01L23/02 , H01L23/00 , H01L25/065 , H01L29/06
CPC分类号： H01L24/02 , H01L24/29 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/80 , H01L24/83 , H01L24/85 , H01L24/92 , H01L25/0657 , H01L29/0657 , H01L2224/04 , H01L2224/04042 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2224/80001 , H01L2224/92165 , H01L2225/06506 , H01L2225/0651 , H01L2924/00014 , H01L2924/10156 , H01L2924/10158 , H01L2924/12042 , H01L2924/15311 , H01L2924/00012 , H01L2924/00 , H01L2224/85399 , H01L2224/05599
摘要： A first semiconductor device die is provided having a bottom edge incorporating a notch structure that allows sufficient height and width clearance for a wire bond connected to a bond pad on an active surface of a second semiconductor device die upon which the first semiconductor device die is stacked. Use of such notch structures reduces a height of a stack incorporating the first and second semiconductor device die, thereby also reducing a thickness of a semiconductor device package incorporating the stack.
摘要翻译：提供第一半导体器件裸片，其具有结合有切口结构的底部边缘，该切口结构允许足够的高度和宽度间隙用于连接到第一半导体器件裸片的第二半导体器件裸片的有源表面上的接合焊盘的引线接合。使用这种切口结构降低了结合第一和第二半导体器件管芯的堆叠的高度，从而也减小了结合堆叠的半导体器件封装的厚度。

46. 发明申请

US20150348595A1 NON-VOLATILE MEMORY USING BI-DIRECTIONAL RESISTIVE ELEMENTS 有权
标题翻译：使用双向电阻元件的非易失性存储器
公开(公告)号：US20150348595A1
公开(公告)日：2015-12-03
申请号：US14287463
申请日：2014-05-27
申请人： Frank K. Baker, JR. , Perry H. Pelley , Ravindraraj Ramaraju
发明人： Frank K. Baker, JR. , Perry H. Pelley , Ravindraraj Ramaraju
IPC分类号： G11C5/06 , G11C13/00
CPC分类号： G11C5/06 , G11C5/025 , G11C5/063 , G11C5/14 , G11C13/0004 , G11C13/0011 , G11C13/0021 , G11C13/0023 , G11C13/0026 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2013/0073 , G11C2213/74 , G11C2213/79 , G11C2213/82
摘要： A memory cell includes a first bi-directional resistive element having a cathode coupled to a first power rail and an anode coupled to an internal node, a second bi-directional resistive element having a cathode coupled to the internal node and an anode coupled to a second power rail, and a first transistor having a control electrode coupled to the internal node, a first current electrode coupled to a first bitline, and a second current electrode coupled to a third power rail.
摘要翻译：存储单元包括具有耦合到第一电源轨的阴极和耦合到内部节点的阳极的第一双向电阻元件，具有耦合到内部节点的阴极的第二双向电阻元件和耦合到内部节点的阳极第二电源轨，以及具有耦合到所述内部节点的控制电极的第一晶体管，耦合到第一位线的第一电流电极和耦合到第三电力轨的第二电流电极。

47. 发明申请

US20150302939A1 MEMORY WITH REDUNDANCY 有权
标题翻译：记忆与冗余
公开(公告)号：US20150302939A1
公开(公告)日：2015-10-22
申请号：US14258730
申请日：2014-04-22
申请人： GEORGE P. HOEKSTRA , Perry H. Pelley , Ravindraraj Ramaraju
发明人： GEORGE P. HOEKSTRA , Perry H. Pelley , Ravindraraj Ramaraju
IPC分类号： G11C29/00 , G11C29/12
CPC分类号： G11C29/44 , G11C29/12 , G11C29/83
摘要： Structures for substituting single bits in an array may include a first array having a plurality of word lines, and for each of the plurality of word lines a memory operable to store a bit substitution column value, and a first data output line operable to communicate the bit substitution column value to a write data shifter. The bit substitution column value may be associated with a bit substitution column in a second array, and the write data shifter may be operable to substitute the bit by shifting data to a redundancy column in the first array.
摘要翻译：用于替换阵列中的单个比特的结构可以包括具有多个字线的第一阵列，并且对于多个字线中的每一个，可操作以存储比特替换列值的存储器和可操作以传达第位替换列值写入数据移位器。比特替换列值可以与第二阵列中的比特替换列相关联，并且写入数据移位器可以用于通过将数据移位到第一阵列中的冗余列来替换该比特。

48. 发明申请

US20150054562A1 LEVEL SHIFTER WITH STATIC PRECHARGE CIRCUIT 有权
标题翻译：带静态预置电路的电平变换器
公开(公告)号：US20150054562A1
公开(公告)日：2015-02-26
申请号：US13972284
申请日：2013-08-21
申请人： Perry H. Pelley
发明人： Perry H. Pelley
IPC分类号： H03K19/0175
CPC分类号： H03K19/0175 , H03K3/356173
摘要： A level shifter includes a static precharge circuit. During a precharge phase, two nodes of the level shifter are precharged to a voltage at or near a reference voltage. During an evaluate phase, the level shifter maintains one of the nodes at the precharge voltage, while the other node is pulled to a different voltage level, such as at or near a ground voltage level, wherein the node that is maintained is selected based on the state of data input signals of the level shifter. The voltage at the nodes determines the state of the level shifter output signals, such that the output signals represent the input signals at a shifted voltage level. The level shifter can include a capacitor to feed forward a signal that causes the precharging to terminate more quickly.
摘要翻译：电平移位器包括静态预充电电路。在预充电阶段期间，电平移位器的两个节点被预充电到等于或接近参考电压的电压。在评估阶段期间，电平移位器将节点中的一个维持在预充电电压，而另一个节点被拉到不同的电压电平，例如在或接近地电压电平，其中维护的节点是基于电平移位器的数据输入信号的状态。节点处的电压确定电平移位器输出信号的状态，使得输出信号表示处于移位电压电平的输入信号。电平移位器可以包括用于馈送使得预充电更快地终止的信号的电容器。

49. 发明授权

US08611128B2 ROM memory device 有权
标题翻译： ROM存储设备
公开(公告)号：US08611128B2
公开(公告)日：2013-12-17
申请号：US12907676
申请日：2010-10-19
申请人： Perry H. Pelley
发明人： Perry H. Pelley
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C17/18
摘要： A memory device includes a plurality of read only memory cells, a precharge circuit, and a sense amplifier. A read only memory (ROM) cell of the plurality of ROM cells is coupled to a word line and a bit line. The ROM cell comprises a transistor having a first current electrode coupled to receive a reference voltage, a second current electrode selectively coupled to the bit line based on the programmed state of the ROM cell, and a control electrode coupled to the word line. The precharge circuit is coupled to the bit line. The precharge circuit precharges the bit line to a precharge voltage, wherein the precharge voltage is less than the reference voltage. The sense amplifier is coupled to the bit line and to a power supply voltage terminal for receiving a power supply voltage, wherein the reference voltage is less than the power supply voltage.
摘要翻译：存储器件包括多个只读存储器单元，预充电电路和读出放大器。多个ROM单元的只读存储器（ROM）单元耦合到字线和位线。 ROM单元包括晶体管，其具有耦合以接收参考电压的第一电流电极，基于ROM单元的编程状态选择性地耦合到位线的第二电流电极，以及耦合到字线的控制电极。预充电电路耦合到位线。预充电电路将位线预充电到预充电电压，其中预充电电压小于参考电压。感测放大器耦合到位线和用于接收电源电压的电源电压端子，其中参考电压小于电源电压。

50. 发明申请

US20130320480A1 METHODS AND STRUCTURES FOR REDUCING HEAT EXPOSURE OF THERMALLY SENSITIVE SEMICONDUCTOR DEVICES 有权
标题翻译：减少热敏半导体器件热暴露的方法和结构
公开(公告)号：US20130320480A1
公开(公告)日：2013-12-05
申请号：US13485886
申请日：2012-05-31
申请人： Michael B. Mcshane , Kevin J. Hess , Perry H. Pelley , Tab A. Stephens
发明人： Michael B. Mcshane , Kevin J. Hess , Perry H. Pelley , Tab A. Stephens
IPC分类号： H01L29/66 , H01L21/768
CPC分类号： H01L23/367 , H01L23/13 , H01L23/3107 , H01L27/10897 , H01L2224/32245 , H01L2224/48091 , H01L2224/4824 , H01L2224/73265 , H01L2924/15311 , H01L2924/00014
摘要： A semiconductor device comprises an integrated circuit (IC) die having a top side and a back side. The circuit substrate includes a heat source circuit, a heat sensitive circuit, a package substrate coupled to the top side of the circuit substrate, and a plurality of thermally conductive through-silicon vias (TSVs) formed from the back side of the circuit substrate to near but not through the top side of the circuit substrate.
摘要翻译：半导体器件包括具有顶侧和背面的集成电路（IC）模具。电路基板包括热源电路，热敏电路，耦合到电路基板的顶侧的封装基板和从电路基板的背面形成的多个导热通硅通孔（TSV）靠近而不是通过电路基板的顶侧。

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