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41. 发明授权

US08115302B2 Electronic module with carrier substrates, multiple integrated circuit (IC) chips and microchannel cooling device 有权
标题翻译：具有载体基板的电子模块，多个集成电路（IC）芯片和微通道冷却装置
公开(公告)号：US08115302B2
公开(公告)日：2012-02-14
申请号：US12134873
申请日：2008-06-06
申请人： Paul S. Andry , Evan G. Colgan
发明人： Paul S. Andry , Evan G. Colgan
IPC分类号： H01L23/473
CPC分类号： H01L23/473 , H01L25/0657 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2225/06517 , H01L2225/06589 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/15311 , H01L2224/0401
摘要： Apparatus and methods are provided for integrating microchannel cooling modules within high-density electronic modules (e.g., chip packages, system-on-a-package modules, etc.,) comprising multiple high-performance IC chips. Electronic modules are designed such that high-performance (high power) IC chips are disposed in close proximity to the integrated cooling module (or cooling plate) for effective heat extraction. Moreover, electronic modules which comprise large surface area silicon carriers with multiple chips face mounted thereon are designed such that integrated silicon cooling modules are rigidly bonded to the back surfaces of such chips to increase the structural integrity of the silicon carriers.
摘要翻译：提供了用于将微通道冷却模块集成在包括多个高性能IC芯片的高密度电子模块（例如，芯片封装，系统级封装模块等）中的装置和方法。电子模块被设计成使得高性能（大功率）IC芯片被布置成靠近集成冷却模块（或冷却板）以有效地提取热量。此外，包括具有多个芯片面的大表面积硅载体的电子模块被设计成使得集成的硅冷却模块刚性地结合到这种芯片的背面以增加硅载体的结构完整性。

42. 发明申请

US20110044369A1 SILICON CARRIER OPTOELECTRONIC PACKAGING 有权
标题翻译：硅载体光电包装
公开(公告)号：US20110044369A1
公开(公告)日：2011-02-24
申请号：US12544696
申请日：2009-08-20
申请人： Paul S. Andry , Russell A. Budd , Bing Dang , David Danovitch , Benjamin V. Fasano , Paul Fortier , Luc Guerin , Frank R. Libsch , Sylvain Ouimet , Chirag S. Patel
发明人： Paul S. Andry , Russell A. Budd , Bing Dang , David Danovitch , Benjamin V. Fasano , Paul Fortier , Luc Guerin , Frank R. Libsch , Sylvain Ouimet , Chirag S. Patel
IPC分类号： H01S5/18 , H01L31/0232 , H01L23/34 , H01L21/50
CPC分类号： H01L27/1446 , G02B6/4204 , G02B6/4249 , G02B6/4257 , G02B6/428 , G02B6/4292 , H01L23/367 , H01L25/16 , H01L27/14625 , H01L2224/131 , H01L2224/16225 , H01L2224/16227 , H01L2224/73253 , H01L2924/01019 , H01L2924/01046 , H01L2924/10253 , H01L2924/14 , H01L2924/1433 , H01L2924/15153 , H01L2924/15192 , H01L2924/15311 , H01L2924/3011 , H01S5/005 , H01S5/0224 , H01S5/02248 , H01S5/02276 , H01S5/02284 , H01S5/02407 , H01S5/02476 , H01S5/183 , H01S5/423 , H01L2924/014 , H01L2924/00
摘要： An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.
摘要翻译：公开了一种用于制造的光电（OE）封装或系统和方法，其包括具有布线的硅层。硅层具有允许光通过的光通孔。光耦合层结合到硅层，并且光耦合层包括多个微透镜，用于聚焦和/或准直光穿过光通孔。多个OE元件耦合到硅层并与布线电连通。至少一个OE元件被定位成与用于接收光的光通孔光学对准。载体介于电互连元件之间。载体位于硅层的布线和电路板之间，并且载体电连接到连接到硅层的布线的第一互连元件和连接到电路板的第二互连元件。

43. 发明授权

US07316831B2 Tilted vertical alignment of liquid crystals employing inorganic thin film composition and ion beam treatment 有权
标题翻译：使用无机薄膜组合物和离子束处理的液晶倾斜垂直取向
公开(公告)号：US07316831B2
公开(公告)日：2008-01-08
申请号：US10706842
申请日：2003-11-12
申请人： Paul S. Andry , Praveen Chaudhari , James P. Doyle , Eileen A. Galligan , James A. Lacey , Shui-Chih A. Lien , Minhua Lu
发明人： Paul S. Andry , Praveen Chaudhari , James P. Doyle , Eileen A. Galligan , James A. Lacey , Shui-Chih A. Lien , Minhua Lu
IPC分类号： G02F1/1337
CPC分类号： G02F1/133734 , G02F1/13378 , G02F2001/133765 , Y10T428/1009
摘要： A liquid crystal display device includes an alignment layer with constituent materials. The constituent materials have a stoichiometric relationship configured to provide a given pretilt angle. Liquid crystal material is provided in contact with the alignment layer. A method for forming an alignment layer for liquid crystal displays includes forming the alignment layer on a substrate by introducing an amount of material to adjust a stoichiometric ratio of constituent materials wherein the amount is determined to provide a given pretilt angle to the alignment layer. Ions are directed at the alignment layer to provide uniformity of the pretilt angle.
摘要翻译：液晶显示装置包括具有构成材料的取向层。构成材料具有配置成提供给定预倾角的化学计量关系。液晶材料设置成与取向层接触。用于形成液晶显示器取向层的方法包括：通过引入一定量的材料在基板上形成取向层，以调整其中所确定的量与取向层提供给定的预倾角的构成材料的化学计量比。离子被引导到对准层以提供预倾角的均匀性。

44. 发明授权

US06566687B2 Metal induced self-aligned crystallization of Si layer for TFT 有权
标题翻译： TFT的Si层的金属诱导自对准结晶
公开(公告)号：US06566687B2
公开(公告)日：2003-05-20
申请号：US09765134
申请日：2001-01-18
申请人： Paul S. Andry , Frank R. Libsch , Takatoshi Tsujimura
发明人： Paul S. Andry , Frank R. Libsch , Takatoshi Tsujimura
IPC分类号： H01L2904
CPC分类号： H01L29/78633 , H01L21/0237 , H01L21/02532 , H01L21/02672 , H01L27/12 , H01L27/1277 , H01L29/66757
摘要： The present invention discloses a semiconductor device, a thin film transistor (TFT), and a process for forming a TFT. The semiconductor device according to the present invention comprises a top-gate type thin film transistor (TFT), said top-gate type TFT being formed on a substrate, said top-gate type TFT comprising: an insulating layer deposited on said substrate; a source electrode and a drain electrode formed from a metal-dopant compound, said metal-dopant compound being deposited on said insulating layer; a polycrystalline Si (poly-Si) layer deposited on said insulating layer and said source electrode and said drain electrode; an ohmic contact layer being formed between said metal-dopant compound and said poly-Si layer through migration of said dopant from said metal-dopant compound; a gate insulating layer deposited on said poly-Si layer; and a gate electrode formed on said gate insulating layer, wherein said poly-Si layer is crystallized by metal induced lateral crystallization.
摘要翻译：本发明公开了半导体器件，薄膜晶体管（TFT）和TFT的形成工艺。根据本发明的半导体器件包括顶栅型薄膜晶体管（TFT），所述顶栅型TFT形成在衬底上，所述顶栅型TFT包括：沉积在所述衬底上的绝缘层; 由金属 - 掺杂剂化合物形成的源电极和漏电极，所述金属 - 掺杂剂化合物沉积在所述绝缘层上; 沉积在所述绝缘层和所述源电极和所述漏电极上的多晶Si（多晶硅）层; 通过所述掺杂剂从所述金属掺杂剂化合物的迁移，在所述金属 - 掺杂剂化合物和所述多晶硅层之间形成欧姆接触层; 沉积在所述多晶硅层上的栅极绝缘层; 以及形成在所述栅极绝缘层上的栅电极，其中所述多晶硅层通过金属诱导的横向结晶而结晶。

45. 发明申请

US20120279287A1 Transferable Probe Tips 有权
标题翻译：可转移探头技巧
公开(公告)号：US20120279287A1
公开(公告)日：2012-11-08
申请号：US13101253
申请日：2011-05-05
申请人： Paul S. Andry , Bing Dang , Steven L. Wright
发明人： Paul S. Andry , Bing Dang , Steven L. Wright
IPC分类号： G01B5/28 , B05D5/00 , C23F1/00
CPC分类号： G01B5/28 , B81B2201/12 , B81C3/001 , B81C2201/0194 , G01Q40/02 , G01Q70/14 , G01Q70/16 , G01R1/067 , G01R1/06738 , G01R1/07378 , G01R3/00 , G03F7/00
摘要： Transferable probe tips including a metallic probe, a delamination layer covering a portion of the metallic probe, and a bonding alloy, wherein the bonding alloy contacts the metallic probe at a portion of the probe that is not covered by the delamination layer are provided herein. Also, techniques for creating a transferable probe tip are provided, including etching a handler substrate to form one or more via arrays, depositing a delamination layer in each via array, depositing one or more metals in each via array to form a probe tip structure, and depositing a bonding alloy on a portion of the probe tip structure that is not covered by the delamination layer. Additionally, techniques for transferring transferable probe tips are provided, including removing a handler substrate from a probe tip structure, and transferring the probe tip structure via flip-chip joining the probe tip structure to a target probe head substrate.
摘要翻译：本发明提供了包括金属探针，覆盖金属探针的一部分的分层和可接合的探针尖端，以及接合合金，其中接合合金在探针的未被分层的覆盖部分处接触金属探针。此外，提供了用于产生可转移探针尖端的技术，包括蚀刻处理器衬底以形成一个或多个通孔阵列，在每个通孔阵列中沉积分层，在每个通孔阵列中沉积一个或多个金属以形成探针尖端结构，以及在未被分层层覆盖的探针尖端结构的一部分上沉积接合合金。此外，提供了用于传送可转移的探针尖端的技术，包括从探针尖端结构去除处理器基底，以及通过将探针尖端结构连接到目标探针头基底的倒装芯片来传送探针尖端结构。

46. 发明申请

US20110205708A1 DOUBLE-FACE HEAT REMOVAL OF VERTICALLY INTEGRATED CHIP-STACKS UTILIZING COMBINED SYMMETRIC SILICON CARRIER FLUID CAVITY AND MICRO-CHANNEL COLD PLATE 有权
标题翻译：使用组合的对称硅载体流体孔和微通道冷板的垂直集成芯片堆的双面加热去除
公开(公告)号：US20110205708A1
公开(公告)日：2011-08-25
申请号：US12711455
申请日：2010-02-24
申请人： Paul S. Andry , Thomas J. Brunschwiler , Evan G. Colgan , John H. Magerlein
发明人： Paul S. Andry , Thomas J. Brunschwiler , Evan G. Colgan , John H. Magerlein
IPC分类号： H05K7/20 , H01L21/50
CPC分类号： H01L23/473 , H01L23/147 , H01L23/3677 , H01L23/481 , H01L23/49827 , H01L25/0657 , H01L2224/16225 , H01L2224/16227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06589 , H01L2924/00014 , H01L2924/10253 , H01L2924/15311 , H01L2924/00 , H01L2224/0401
摘要： A plurality of heat-dissipating electronic chips are arranged in a vertical chip stack. The electronic chips have electronic components thereon. A cold plate is secured to a back side of the chip stack. A silicon carrier sandwich, defining a fluid cavity, is secured to a front side of the chip stack. An inlet manifold is configured to supply cooling fluid to the cold plate and the fluid cavity of the silicon carrier sandwich. An outlet manifold is configured to receive the cooling fluid from the cold plate and the fluid cavity of the silicon carrier sandwich. The cold plate, the silicon carrier sandwich, the inlet manifold, and the outlet manifold are configured and dimensioned to electrically isolate the cooling fluid from the electronic components. A method of operating an electronic apparatus and a method of manufacturing an electronic apparatus are also disclosed. Single-sided heat removal with double-sided electrical input-output and double-sided heat removal with double-sided electrical input-output are also disclosed.
摘要翻译：多个散热电子芯片布置在垂直芯片堆叠中。电子芯片上有电子部件。冷板固定在芯片堆叠的背面。限定流体腔的硅载体夹层固定到芯片组的前侧。入口歧管构造成将冷却流体供应到冷却板和硅载体三明治的流体腔。出口歧管构造成从冷板和硅载体三明治的流体腔接收冷却流体。冷板，硅载体夹层，入口歧管和出口歧管的构造和尺寸被设计成将冷却流体与电子部件电隔离。还公开了操作电子设备的方法和制造电子设备的方法。还公开了具有双面电输入输出和双面电输入输出的双面除热的单面除热。

47. 发明授权

US07990711B1 Double-face heat removal of vertically integrated chip-stacks utilizing combined symmetric silicon carrier fluid cavity and micro-channel cold plate 有权
标题翻译：使用组合的对称硅载体流体腔和微通道冷板的垂直集成芯片堆叠的双面散热
公开(公告)号：US07990711B1
公开(公告)日：2011-08-02
申请号：US12711455
申请日：2010-02-24
申请人： Paul S. Andry , Thomas J. Brunschwiler , Evan G. Colgan , John H. Magerlein
发明人： Paul S. Andry , Thomas J. Brunschwiler , Evan G. Colgan , John H. Magerlein
IPC分类号： H05K7/20
CPC分类号： H01L23/473 , H01L23/147 , H01L23/3677 , H01L23/481 , H01L23/49827 , H01L25/0657 , H01L2224/16225 , H01L2224/16227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06589 , H01L2924/00014 , H01L2924/10253 , H01L2924/15311 , H01L2924/00 , H01L2224/0401
摘要： A plurality of heat-dissipating electronic chips are arranged in a vertical chip stack. The electronic chips have electronic components thereon. A cold plate is secured to a back side of the chip stack. A silicon carrier sandwich, defining a fluid cavity, is secured to a front side of the chip stack. An inlet manifold is configured to supply cooling fluid to the cold plate and the fluid cavity of the silicon carrier sandwich. An outlet manifold is configured to receive the cooling fluid from the cold plate and the fluid cavity of the silicon carrier sandwich. The cold plate, the silicon carrier sandwich, the inlet manifold, and the outlet manifold are configured and dimensioned to electrically isolate the cooling fluid from the electronic components. A method of operating an electronic apparatus and a method of manufacturing an electronic apparatus are also disclosed. Single-sided heat removal with double-sided electrical input-output and double-sided heat removal with double-sided electrical input-output are also disclosed.
摘要翻译：多个散热电子芯片布置在垂直芯片堆叠中。电子芯片上有电子部件。冷板固定在芯片堆叠的背面。限定流体腔的硅载体夹层固定到芯片组的前侧。入口歧管构造成将冷却流体供应到冷却板和硅载体三明治的流体腔。出口歧管构造成从冷板和硅载体三明治的流体腔接收冷却流体。冷板，硅载体夹层，入口歧管和出口歧管的构造和尺寸被设计成将冷却流体与电子部件电隔离。还公开了操作电子设备的方法和制造电子设备的方法。还公开了具有双面电输入输出和双面电输入输出的双面除热的单面除热。

48. 发明申请

US20080315403A1 APPARATUS AND METHODS FOR COOLING SEMICONDUCTOR INTEGRATED CIRCUIT CHIP PACKAGES 有权
标题翻译：用于冷却半导体集成电路芯片封装的装置和方法
公开(公告)号：US20080315403A1
公开(公告)日：2008-12-25
申请号：US12134883
申请日：2008-06-06
申请人： Paul S. Andry , Evan G. Colgan , Lawrence S. Mok , Chirag S. Patel , David E. Seeger
发明人： Paul S. Andry , Evan G. Colgan , Lawrence S. Mok , Chirag S. Patel , David E. Seeger
IPC分类号： H01L23/46
CPC分类号： H01L23/473 , H01L25/0657 , H01L2224/16225 , H01L2224/32245 , H01L2224/73253 , H01L2225/06517 , H01L2225/06589 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/15311 , H01L2224/0401
摘要： Apparatus and methods are provided for integrating microchannel cooling modules within high-density electronic modules (e.g., chip packages, system-on-a-package modules, etc.,) comprising multiple high-performance IC chips. Electronic modules are designed such that high-performance (high power) IC chips are disposed in close proximity to the integrated cooling module (or cooling plate) for effective heat extraction. Moreover, electronic modules which comprise large surface area silicon carriers with multiple chips face mounted thereon are designed such that integrated silicon cooling modules are rigidly bonded to the back surfaces of such chips to increase the structural integrity of the silicon carriers.
摘要翻译：提供了用于将微通道冷却模块集成在包括多个高性能IC芯片的高密度电子模块（例如，芯片封装，系统级封装模块等）中的装置和方法。电子模块被设计成使得高性能（大功率）IC芯片被布置成靠近集成冷却模块（或冷却板）以有效地提取热量。此外，包括具有多个芯片面的大表面积硅载体的电子模块被设计成使得集成的硅冷却模块刚性地结合到这种芯片的背面以增加硅载体的结构完整性。

49. 发明授权

US06767828B2 Method for forming patterns for semiconductor devices 有权
标题翻译：用于形成半导体器件的图案的方法
公开(公告)号：US06767828B2
公开(公告)日：2004-07-27
申请号：US09971953
申请日：2001-10-05
申请人： Paul S. Andry , John C. Flake , Bruno Michel , Takatoshi Tsujimura
发明人： Paul S. Andry , John C. Flake , Bruno Michel , Takatoshi Tsujimura
IPC分类号： H01L2144
CPC分类号： H01L28/60 , H01L21/288 , H01L21/76841 , H01L28/55 , H01L2924/0002 , H05K3/182 , H05K3/389 , Y10T428/24926 , H01L2924/00
摘要： A method for forming an electrically conductive layer having predetermined patterns for semiconductor devices includes providing a substrate, forming an insulation layer having OH functional groups on the substrate, forming a patterned polymer layer on the insulation layer, etching the insulation layer to create a patterned insulation layer which has the same patterns as the patterned polymer layer, stripping the patterned polymer layer to expose the patterned insulation layer, treating the patterned insulation layer with a coupling agent which reacts with the OH functional groups, treating the patterned insulation layer with a catalyst-containing solution in which the catalyst reacts with the coupling agent, and depositing electrically conductive material on the patterned insulation layer which is catalytically active.
摘要翻译：一种用于形成具有用于半导体器件的具有预定图案的导电层的方法包括提供衬底，在衬底上形成具有OH官能团的绝缘层，在绝缘层上形成图案化聚合物层，蚀刻绝缘层以产生图案绝缘层，其具有与图案化聚合物层相同的图案，剥离图案化的聚合物层以暴露图案化绝缘层，用与OH官能团反应的偶联剂处理图案化绝缘层，用催化剂层处理图案化绝缘层，其中催化剂与偶联剂反应，并且将导电材料沉积在具有催化活性的图案化绝缘层上。

50. 发明授权

US06731361B2 High resolution in-plane switching mode TFT-LCD 有权
标题翻译：高分辨率的平面内切换模式TFT-LCD
公开(公告)号：US06731361B2
公开(公告)日：2004-05-04
申请号：US09876382
申请日：2001-06-07
申请人： Paul S. Andry , Praveen Chaudhari , James P. Doyle , Eileen A. Galligan , Richard A. John , James A. Lacey , Shui-Chih A. Lien , Minhua Lu
发明人： Paul S. Andry , Praveen Chaudhari , James P. Doyle , Eileen A. Galligan , Richard A. John , James A. Lacey , Shui-Chih A. Lien , Minhua Lu
IPC分类号： G02F11333
CPC分类号： G02F1/134363
摘要： Display panels and methods for fabrication are disclosed for an in-plane switching mode display to reduce or eliminate image sticking. The display panel includes a substrate with a first electrode formed on the substrate. A dielectric layer is formed on the substrate, and the dielectric layer forms an opening down to the first electrode so that the dielectric layer is eliminated over the first electrode. A second electrode is formed on the dielectric layer, and an alignment layer is formed on the first electrode, the second electrode and the dielectric layer.
摘要翻译：公开了用于制造的显示面板和方法用于面内切换模式显示以减少或消除图像残留。显示面板包括在基板上形成有第一电极的基板。在基板上形成电介质层，电介质层形成向下延伸到第一电极的开口，从而在第一电极上消除电介质层。在电介质层上形成第二电极，在第一电极，第二电极和电介质层上形成取向层。

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