专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明申请

US20090039472A1 STRUCTURE AND METHOD FOR CREATING RELIABLE DEEP VIA CONNECTIONS IN A SILICON CARRIER 有权
标题翻译：通过硅载体连接创造可靠深度的结构和方法
公开(公告)号：US20090039472A1
公开(公告)日：2009-02-12
申请号：US12147466
申请日：2008-06-26
申请人： Paul S. Andry , John U. Knickerbocker , Michelle L. Steen , Cornelia K. Tsang
发明人： Paul S. Andry , John U. Knickerbocker , Michelle L. Steen , Cornelia K. Tsang
IPC分类号： H01L23/538 , H01L21/768
CPC分类号： H01L23/49827 , H01L21/486 , H01L21/76898 , H01L23/147 , H01L2924/0002 , H01L2924/00
摘要： A process and structure for enabling the creation of reliable electrical through-via connections in a semiconductor substrate and a process for filling vias. Problems associated with under etch, over etch and flaring of deep Si RIE etched through-vias are mitigated, thereby vastly improving the integrity of the insulation and metallization layers used to convert the through-vias into highly conductive pathways across the Si wafer thickness. By using an insulating collar structure in the substrate in one case and by filling the via in accordance with the invention in another case, whole wafer yield of electrically conductive through vias is greatly enhanced.
摘要翻译：一种用于在半导体衬底中创建可靠的电通孔连接的工艺和结构以及用于填充过孔的工艺。与深蚀刻Si RIE蚀刻通孔相切的蚀刻，过蚀刻和扩散相关的问题得到缓解，从而大大提高了用于将通孔转换成穿过Si晶片厚度的高导电通路的绝缘层和金属化层的完整性。通过在一种情况下通过在衬底中使用绝缘套环结构，并且在另一种情况下通过填充根据本发明的通孔，大大增强了导电通孔的整个晶片产量。

42. 发明申请

US20080284037A1 Apparatus and Methods for Constructing Semiconductor Chip Packages with Silicon Space Transformer Carriers 审中-公开
标题翻译：使用硅空间变压器载体构建半导体芯片封装的装置和方法
公开(公告)号：US20080284037A1
公开(公告)日：2008-11-20
申请号：US11748818
申请日：2007-05-15
申请人： Paul S. Andry , John M. Cotte , John U. Knickerbocker , Cornelia K. Tsang
发明人： Paul S. Andry , John M. Cotte , John U. Knickerbocker , Cornelia K. Tsang
IPC分类号： H01L23/48 , H01L21/00
CPC分类号： H01L21/6835 , H01L23/147 , H01L23/49827 , H01L23/49833 , H01L23/50 , H01L24/81 , H01L25/0655 , H01L25/0657 , H01L2221/68345 , H01L2224/16225 , H01L2224/81801 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/01077 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3025 , H01L2924/00 , H01L2224/0401
摘要： Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration.
摘要翻译：提供了用于使用硅空间变压器芯片级封装结构的半导体芯片的高密度封装的装置和方法，其允许高密度芯片互连和/或多个芯片或芯片堆叠的高I / O互连和异构芯片或功能集成。

43. 发明授权

US09159602B2 Apparatus and methods for constructing semiconductor chip packages with silicon space transformer carriers 有权
标题翻译：用硅空间变压器承载构造半导体芯片封装的装置和方法
公开(公告)号：US09159602B2
公开(公告)日：2015-10-13
申请号：US12543827
申请日：2009-08-19
申请人： Paul S. Andry , John M. Cotte , John U. Knickerbocker , Cornelia K. Tsang
发明人： Paul S. Andry , John M. Cotte , John U. Knickerbocker , Cornelia K. Tsang
IPC分类号： H01L23/02 , H01L21/683 , H01L23/14 , H01L23/498 , H01L23/50 , H01L23/00 , H01L25/065
CPC分类号： H01L21/6835 , H01L23/147 , H01L23/49827 , H01L23/49833 , H01L23/50 , H01L24/81 , H01L25/0655 , H01L25/0657 , H01L2221/68345 , H01L2224/16225 , H01L2224/81801 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/01077 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3025 , H01L2924/00 , H01L2224/0401
摘要： Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration.
摘要翻译：提供了用于使用硅空间变压器芯片级封装结构的半导体芯片的高密度封装的装置和方法，其允许高密度芯片互连和/或多个芯片或芯片堆叠的高I / O互连和异构芯片或功能集成。

44. 发明申请

US20120326309A1 OPTIMIZED ANNULAR COPPER TSV 有权
标题翻译：优化的环形铜片TSV
公开(公告)号：US20120326309A1
公开(公告)日：2012-12-27
申请号：US13167107
申请日：2011-06-23
申请人： PAUL S ANDRY , Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Emily R. Kinser , Cornelia K. Tsang , Richard P. Volant
发明人： PAUL S ANDRY , Mukta G. Farooq , Robert Hannon , Subramanian S. Iyer , Emily R. Kinser , Cornelia K. Tsang , Richard P. Volant
IPC分类号： H01L23/48 , H01L21/283
CPC分类号： H01L21/76846 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench.
摘要翻译：本公开提供了热机械可靠的铜TSV和在BEOL处理期间形成这种TSV的技术。 TSV构成延伸穿过半导体衬底的环形沟槽。衬底限定沟槽的内侧壁和外侧壁，该侧壁分隔5至10微米的距离。包括铜或铜合金的导电路径从所述第一介电层的上表面通过所述衬底在所述沟槽内延伸。基板厚度可以为60微米或更小。具有导电连接到导电路径的互连金属化的电介质层直接形成在所述环形沟槽上。

45. 发明申请

US20120181648A1 APPARATUS AND METHODS FOR CONSTRUCTING SEMICONDUCTOR CHIP PACKAGES WITH SILICON SPACE TRANSFORMER CARRIERS 有权
标题翻译：用硅空间变压器构造半导体芯片包装的装置和方法
公开(公告)号：US20120181648A1
公开(公告)日：2012-07-19
申请号：US13430195
申请日：2012-03-26
申请人： PAUL S. ANDRY , John M. Cotte , John U. Knickerbocker , Cornelia K. Tsang
发明人： PAUL S. ANDRY , John M. Cotte , John U. Knickerbocker , Cornelia K. Tsang
IPC分类号： H01L23/48 , H01L31/0232
CPC分类号： H01L21/6835 , H01L23/147 , H01L23/49827 , H01L23/49833 , H01L23/50 , H01L24/81 , H01L25/0655 , H01L25/0657 , H01L2221/68345 , H01L2224/16225 , H01L2224/81801 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/01077 , H01L2924/01079 , H01L2924/10253 , H01L2924/14 , H01L2924/15174 , H01L2924/15311 , H01L2924/19011 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3025 , H01L2924/00 , H01L2224/0401
摘要： Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration.
摘要翻译：提供了用于使用硅空间变压器芯片级封装结构的半导体芯片的高密度封装的装置和方法，其允许高密度芯片互连和/或多个芯片或芯片堆叠的高I / O互连和异构芯片或功能集成。

46. 发明申请

US20090311849A1 METHODS OF SEPARATING INTEGRATED CIRCUIT CHIPS FABRICATED ON A WAFER 审中-公开
标题翻译：在波形上分离集成电路芯片的方法
公开(公告)号：US20090311849A1
公开(公告)日：2009-12-17
申请号：US12140492
申请日：2008-06-17
申请人： Paul S. Andry , Bing Dang , Matthew J. Farinelli , Cornelia K. Tsang
发明人： Paul S. Andry , Bing Dang , Matthew J. Farinelli , Cornelia K. Tsang
IPC分类号： H01L21/00
CPC分类号： H01L21/78 , H01L21/6836 , H01L2221/68327 , H01L2221/68354 , H01L2221/68381 , H01L2224/16 , H01L2924/14
摘要： Improved methods of separating integrated circuit chips fabricated on a single wafer are provided. In an embodiment, a method of separating integrated circuit chips fabricated on a wafer comprises: attaching a support to a back surface of the wafer; dicing the wafer to form individual integrated circuit chips attached to the support; attaching a carrier comprising a releasable adhesive material to a front surface of the wafer opposite from the back surface; separating the support from the back surface of the wafer; subjecting the carrier to an effective amount of heat, radiation, or both to reduce the adhesiveness of the adhesive material to allow for removal of at least one of the integrated circuit chips from the carrier; and picking up and moving at least one of the integrated circuit chips using a tool configured to handle the integrated circuit chips.
摘要翻译：提供了分离在单个晶片上制造的集成电路芯片的改进的方法。在一个实施例中，分离在晶片上制造的集成电路芯片的方法包括：将支撑件附接到晶片的背面; 切割晶片以形成附接到支撑件的单个集成电路芯片; 将包含可释放粘合剂材料的载体附接到所述晶片的与所述后表面相对的前表面; 将支撑体从晶片的背面分离; 使载体经受有效量的热量，辐射或两者以降低粘合剂材料的粘附性，以允许将集成电路芯片中的至少一个从载体上移除; 以及使用构造成处理集成电路芯片的工具来拾取和移动至少一个集成电路芯片。

47. 发明申请

US20090280643A1 OPTIMAL TUNGSTEN THROUGH WAFER VIA AND PROCESS OF FABRICATING SAME 失效
标题翻译：通过WAFER的最佳方式和制作方法
公开(公告)号：US20090280643A1
公开(公告)日：2009-11-12
申请号：US12115568
申请日：2008-05-06
申请人： Paul S. Andry , Edward C. Cooney, III , Peter J. Lindgren , Dorreen J. Ossenkop , Cornelia K. Tsang
发明人： Paul S. Andry , Edward C. Cooney, III , Peter J. Lindgren , Dorreen J. Ossenkop , Cornelia K. Tsang
IPC分类号： H01L23/482 , H01L21/768 , H01L21/44 , H01L23/48 , H01L29/40 , H01L23/52
CPC分类号： H01L23/485 , H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A method of optimally filling a through via within a through wafer via structure with a conductive metal such as, for example, W is provided. The inventive method includes providing a structure including a substrate having at least one aperture at least partially formed through the substrate. The at least one aperture of the structure has an aspect ratio of at least 20:1 or greater. Next, a refractory metal-containing liner such as, for example, Ti/TiN, is formed on bare sidewalls of the substrate within the at least one aperture. A conductive metal seed layer is then formed on the refractory metal-containing liner. In the invention, the conductive metal seed layer formed is enriched with silicon and has a grain size of about 5 nm or less. Next, a conductive metal nucleation layer is formed on the conductive metal seed layer. The conductive metal nucleation layer is also enriched with silicon and has a grain size of about 20 nm or greater. Next, a conductive metal is formed on the conductive metal nucleation layer. After performing the above processing steps, a backside planarization process is performed to convert the at least one aperture into at least one through via that is now optimally filled with a conductive metal.
摘要翻译：提供了一种在具有例如W的导电金属的直通晶片通孔结构内最佳地填充通孔的方法。本发明的方法包括提供一种结构，其包括具有至少一个通过该基底部分形成的孔的基底。该结构的至少一个孔具有至少20:1或更大的纵横比。接下来，在至少一个孔内的衬底的裸露的侧壁上形成诸如Ti / TiN的含难熔金属衬里。然后在含难熔金属的衬垫上形成导电金属种子层。在本发明中，所形成的导电金属晶种层富含硅，其晶粒尺寸为约5nm或更小。接着，在导电性金属种子层上形成导电性金属成核层。导电金属成核层也富含硅，其粒径约为20nm或更大。接着，在导电性金属成核层上形成导电性金属。在执行上述处理步骤之后，执行背面平面化处理以将至少一个孔转换成现在被最佳地填充有导电金属的至少一个通孔。

48. 发明申请

US20090032951A1 Small Area, Robust Silicon Via Structure and Process 有权
标题翻译：小面积，坚固的硅通过结构和工艺
公开(公告)号：US20090032951A1
公开(公告)日：2009-02-05
申请号：US11833112
申请日：2007-08-02
申请人： Paul S. Andry , John M. Cotte , John Ulrich Knickerbocker , Cornelia K. Tsang
发明人： Paul S. Andry , John M. Cotte , John Ulrich Knickerbocker , Cornelia K. Tsang
IPC分类号： H01L21/768 , H01L23/52
CPC分类号： H01L21/76898 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/80 , H01L24/94 , H01L2224/0401 , H01L2224/0557 , H01L2224/13025 , H01L2224/16 , H01L2224/94 , H01L2924/0002 , H01L2924/01006 , H01L2924/01029 , H01L2924/01033 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/1461 , H01L2924/19041 , H01L2924/19042 , H01L2924/30105 , H01L2924/30107 , H01L2224/11 , H01L2924/00 , H01L2224/05552
摘要： A semiconductor structure includes: at least one silicon surface wherein the surface can be a substrate, wafer or other device. The structure further includes at least one electronic circuit formed on each side of the at least one surface; and at least one conductive high aspect ratio through silicon via running through the at least one surface. Each through silicon via is fabricated from at least one etch step and includes: at least one thermal oxide dielectric for coating at least some of a sidewall of the through silicon via for a later etch stop in fabrication of the through silicon via.
摘要翻译：半导体结构包括：至少一个硅表面，其中该表面可以是衬底，晶片或其它器件。该结构还包括形成在至少一个表面的每一侧上的至少一个电子电路; 以及通过硅穿过所述至少一个表面的至少一个导电高宽比。每个通过硅通孔由至少一个蚀刻步骤制造，并且包括：至少一个热氧化物电介质，用于涂覆通孔硅通孔的侧壁中的至少一些，用于随后的通孔硅制造中的蚀刻停止。

49. 发明申请

US20110290402A1 Handler Attachment for Integrated Circuit Fabrication 失效
标题翻译：集成电路制造的处理器附件
公开(公告)号：US20110290402A1
公开(公告)日：2011-12-01
申请号：US12788832
申请日：2010-05-27
申请人： Paul Andry , Bing Dang , John Knickerbocker , Aparna Prabhakar , Peter Sorce , Robert E. Trzcinski , Cornelia K. Tsang
发明人： Paul Andry , Bing Dang , John Knickerbocker , Aparna Prabhakar , Peter Sorce , Robert E. Trzcinski , Cornelia K. Tsang
IPC分类号： B32B33/00 , B29C65/16
CPC分类号： H01L21/67132 , C09J5/06 , C09J2203/326 , C09J2479/08 , H01L21/6835 , H01L2221/6835 , H01L2221/68381 , Y10T156/1158
摘要： A method for attaching a handler to a wafer, the wafer comprising an integrated circuit (IC), includes forming a layer of an adhesive on the wafer, the adhesive comprising a polyimide-based polymer configured to withstand processing at a temperature of over about 280° C.; and adhering a handler to the wafer using the layer of adhesive. A system for attaching a handler to a wafer, the wafer comprising IC, includes a layer of an adhesive located on the wafer, the adhesive comprising a polyimide-based polymer configured to withstand processing at a temperature of over about 280° C.; and a handler adhered to the wafer using the layer of adhesive.
摘要翻译：一种用于将处理器附接到晶片的方法，所述晶片包括集成电路（IC），包括在所述晶片上形成粘合剂层，所述粘合剂包括基于聚酰亚胺的聚合物，所述聚酰亚胺基聚合物构造成经受超过约280℃的温度下的加工 C。; 以及使用所述粘合剂层将处理器粘附到所述晶片。一种用于将处理器附接到晶片的系统，包括IC的晶片包括位于晶片上的粘合剂层，所述粘合剂包括基于聚酰亚胺的聚合物，其被配置为经受超过约280℃的温度下的加工; 以及使用粘合剂层粘附到晶片的处理器。

50. 发明申请

US20110290413A1 Laser Ablation of Adhesive for Integrated Circuit Fabrication 有权
标题翻译：激光烧蚀用于集成电路制造的粘合剂
公开(公告)号：US20110290413A1
公开(公告)日：2011-12-01
申请号：US12788839
申请日：2010-05-27
申请人： Bing Dang , Matthew Farinelli , John Knickerbocker , Aparna Prabhakar , Robert E. Trzcinski , Cornelia K. Tsang
发明人： Bing Dang , Matthew Farinelli , John Knickerbocker , Aparna Prabhakar , Robert E. Trzcinski , Cornelia K. Tsang
IPC分类号： B32B38/10 , B29C65/16
CPC分类号： H01L21/6835 , B23K26/0622 , B23K26/0823 , B23K26/361 , B23K26/57 , B23K2101/40 , B23K2103/42 , B23K2103/50 , C09J5/00 , C09J2203/326 , C09J2205/302 , C09J2400/22 , H01L2221/68381 , Y10T156/1158 , Y10T156/1917
摘要： A method for releasing a handler from a wafer, the wafer comprising an integrated circuit (IC), includes attaching the handler to the wafer using an adhesive comprising a thermoset polymer, the handler comprising a material that is transparent in a wavelength range of about 193 nanometers (nm) to about 400 nm; ablating the adhesive through the handler using a laser, wherein a wavelength of the laser is selected based on the transparency of the handler material; and separating the handler from the wafer.
摘要翻译：一种用于从晶片释放处理器的方法，所述晶片包括集成电路（IC），包括使用包含热固性聚合物的粘合剂将所述处理器附接到所述晶片，所述处理器包括在约193的波长范围内是透明的材料纳米（nm）至约400nm; 使用激光器通过处理器烧蚀粘合剂，其中基于处理材料的透明度选择激光的波长; 并将处理器与晶片分离。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式