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41. 发明申请

US20110148456A1 Method and Device for Measuring Inter-chip Signals 失效
标题翻译：用于测量芯片间信号的方法和装置
公开(公告)号：US20110148456A1
公开(公告)日：2011-06-23
申请号：US12642278
申请日：2009-12-18
申请人： Bart A. MOOYMAN-BECK , Robert J. WOOLHISER , Kevin E. COSGROVE , Daniel G. Knierim
发明人： Bart A. MOOYMAN-BECK , Robert J. WOOLHISER , Kevin E. COSGROVE , Daniel G. Knierim
IPC分类号： G01R31/26 , H05K7/02
CPC分类号： G01R31/318511 , G01R31/318513 , H01L2224/16225 , H01L2225/06596 , H01L2924/15192 , H01L2924/15311 , H01L2924/157
摘要： A method and device for measuring a signal of a die to be placed within a package is disclosed. At least one die as a Device Under Test (DUT) is mounted on a substrate and a chip-type measurement instrument is mounted on the substrate, or embedded into the substrate, wherein the instrument analyzes and/or processes the signal of the DUT and may provide stimulus signal to the DUT. The substrate having the DUT and the measurement instrument is mounted on a circuit board that has plural electrodes to be connected to the signal paths of the DUT and the instrument. An electrode is coupled to a standard interface port to provide the signal of the chip-type instrument to an external instrument.
摘要翻译：公开了一种用于测量待放置在封装内的管芯信号的方法和装置。至少一个裸片作为被测设备（DUT）安装在基板上，芯片式测量仪器安装在基板上或嵌入基板中，其中仪器分析和/或处理DUT的信号，可以向DUT提供刺激信号。具有DUT的基板和测量仪器安装在具有要连接到DUT和仪器的信号路径的多个电极的电路板上。电极耦合到标准接口端口，以将芯片型仪器的信号提供给外部仪器。

42. 发明申请

US20110074441A1 Low Capacitance Signal Acquisition System 审中-公开
标题翻译：低电容信号采集系统
公开(公告)号：US20110074441A1
公开(公告)日：2011-03-31
申请号：US12571236
申请日：2009-09-30
申请人： Josiah A. Bartlett , Ira G. Pollock , Daniel G. Knierim , Lester L. Larson , Scott R. Jansen , Kenneth P. Dobyns , Michael Duane Stevens
发明人： Josiah A. Bartlett , Ira G. Pollock , Daniel G. Knierim , Lester L. Larson , Scott R. Jansen , Kenneth P. Dobyns , Michael Duane Stevens
IPC分类号： G01R35/00 , G01R27/26
CPC分类号： G01R1/06766 , G01R1/06772
摘要： A low capacitance signal acquisition system has a signal acquisition probe having a low capacitance input circuit coupled to a compensation amplifier in a signal processing instrument via a signal cable. The low capacitance input circuit, the signal cable and the signal processing instrument input have mismatched time constants with the compensation amplifier having feedback loop circuitry providing adjustable gain and pole-zero pairs for maintaining flatness over the low capacitance signal acquisition system frequency bandwidth.
摘要翻译：低电容信号采集系统具有信号采集探针，其具有经由信号电缆耦合到信号处理仪器中的补偿放大器的低电容输入电路。低电容输入电路，信号电缆和信号处理仪器输入具有不匹配的时间常数，补偿放大器具有反馈回路电路，提供可调增益和极 - 零对，以保持低电容信号采集系统频率带宽上的平坦度。

43. 发明授权

US5986637A Digital oscilloscope architecture for signal monitoring with enhanced duty cycle 失效
标题翻译：数字示波器架构，用于增强占空比的信号监控
公开(公告)号：US5986637A
公开(公告)日：1999-11-16
申请号：US953225
申请日：1997-10-17
申请人： Eric P. Etheridge , Gordon W. Shank , Daniel G. Knierim
发明人： Eric P. Etheridge , Gordon W. Shank , Daniel G. Knierim
IPC分类号： G01R13/20 , G01R13/02 , G01R13/26 , G01R13/34 , G09G5/36
CPC分类号： G01R13/345 , G01R13/0227 , G01R13/26
摘要： To increase the percentage of time that an input signal is actively monitored, a digital oscilloscope has an acquisition system (100) that includes an analog-to-digital converter (15), an acquisition memory (40), an acquisition rasterizer (50), and a raster acquisition memory (60). The rasterizer contains circuitry (52) for concurrently rasterizing and combining the results of several acquisitions together and with a stored composite raster image to produce a new composite raster image, while additional acquisition records are being created and stored in the acquisition memory. A display system 200 takes the composite raster images after they contain the results of many acquisitions and overlays these single-bit raster images on a multi-bit raster image that is then decremented to produce a simulated persistence effect. The number of new pixels turned on as a result of each acquisition can be counted during the combining process and used to stop acquisitions, signal the operator, or specially treat that particular acquisition when the number of new pixels created by a particular acquisition exceeds a predetermined value. Acquisition circuitry for multiple channels can be used on one channel to further increase the percentage of time that the signal is monitored.
摘要翻译：为了增加主动监测输入信号的时间百分比，数字示波器具有采集系统（100），其包括模数转换器（15），采集存储器（40），采集光栅化器（50），以及光栅采集存储器（60）。光栅化器包括电路（52），用于同时光栅化并将多个采集的结果组合在一起并与存储的复合光栅图像组合以产生新的复合光栅图像，同时另外获取记录被创建并存储在采集存储器中。显示系统200在它们包含多次获取的结果并且将这些单位光栅图像叠加在多位光栅图像上之后取得复合光栅图像，然后将其减少以产生模拟的持续效果。作为每次获取的结果而打开的新像素的数量可以在组合处理期间被计数，并且用于停止采集，向操作者发信号，或者当由特定采集创建的新像素的数量超过预定值时特别处理该特定采集值。可以在一个通道上使用多个通道的采集电路，以进一步增加监控信号的时间百分比。

44. 发明授权

US5418533A Method and circuit for conditioning a signal for use in systems having analog-to-digital converter circuits 失效
标题翻译：用于调节用于具有模数转换器电路的系统中的信号的方法和电路
公开(公告)号：US5418533A
公开(公告)日：1995-05-23
申请号：US155401
申请日：1993-11-19
申请人： Daniel G. Knierim
发明人： Daniel G. Knierim
IPC分类号： G06F3/05 , G11C27/02 , H03M1/12 , H03M1/00
CPC分类号： H03M1/124
摘要： A method and circuit for conditioning a received analog signal for input to an analog-to-digital converter circuit ("ADC"). For each clock period in which a conversion is triggered, a first analog value is provided during a first predetermined period and a second analog value is provided during a second predetermined period. The first analog value is representative of the received analog signal's instantaneous value at the moment selected for conversion. The second analog value is predetermined, typically being a null value. The signal conditioning circuit includes a hold circuit to hold the received analog signal's instantaneous value; a generating circuit that generates the second analog value; and an output circuit that selectively outputs the instantaneous value or the predetermined value to the ADC. The hold circuit, the generating circuit and the output circuits are synchronized with the clock signal clocking the ADC so that the ADC's input signal aperture is contained or centered, or both, substantially within the first predetermined period.
摘要翻译：一种用于对接收到的模拟信号进行调理以便输入到模拟 - 数字转换器电路（“ADC”）的方法和电路。对于触发转换的每个时钟周期，在第一预定周期期间提供第一模拟值，并且在第二预定周期期间提供第二模拟值。第一个模拟值代表接收到的模拟信号在转换时刻的瞬时值。第二模拟值是预定的，通常是空值。信号调理电路包括保持电路以保持所接收的模拟信号的瞬时值; 产生所述第二模拟值的发电电路; 以及选择性地向ADC输出瞬时值或预定值的输出电路。保持电路，发生电路和输出电路与时钟信号ADC同步，使得ADC的输入信号孔径被包含或居中或基本上在第一预定周期内。

45. 发明授权

US5406507A Reduced input capacitance analog storage array 失效
标题翻译：降低输入电容模拟存储阵列
公开(公告)号：US5406507A
公开(公告)日：1995-04-11
申请号：US65011
申请日：1993-05-24
申请人： Daniel G. Knierim , Steven K. Sullivan
发明人： Daniel G. Knierim , Steven K. Sullivan
IPC分类号： G11C27/00 , H03K17/00
CPC分类号： G11C27/00
摘要： Reduction of input capacitance in an analog storage array is achieved by reducing the parasitic capacitance presented to an analog signal line. Each column of the analog storage array is coupled to the analog signal line by a separate coupling switch. The switches are activated so that no more than two columns are coupled to the analog signal line at any time, with the next column to be accessed being coupled to the analog signal line prior to access to that column, and the last column being decoupled from the analog signal line after the last cell in the column has been accessed. Further the analog signal line may provide two input ports so that alternate columns of the array are coupled to one port, and the other alternate columns are coupled to the other port so that two adjacent columns are coupled to separate ones of the two ports.
摘要翻译：减少模拟存储阵列中的输入电容可以通过减少呈现给模拟信号线的寄生电容来实现。模拟存储阵列的每一列通过单独的耦合开关耦合到模拟信号线。开关被激活，使得在任何时候不超过两个列耦合到模拟信号线，下一个待访问的列在访问该列之前耦合到模拟信号线，并且最后一列被解耦列中最后一个单元格后的模拟信号线已被访问。此外，模拟信号线可以提供两个输入端口，使得阵列的备用列耦合到一个端口，而另一个备用列耦合到另一个端口，使得两个相邻列耦合以分离两个端口中的一个。

46. 发明授权

US4733220A Thermometer-to-adjacent bindary encoder 失效
标题翻译：温度计相邻的带编码器
公开(公告)号：US4733220A
公开(公告)日：1988-03-22
申请号：US920936
申请日：1986-10-20
申请人： Daniel G. Knierim
发明人： Daniel G. Knierim
IPC分类号： H03M1/36 , H03M7/16
CPC分类号： H03M1/36 , H03M7/165
摘要： An encoder circuit converts a thermometer code into an equivalent adjacent binary code wherein only a single bit is changed to minimally increment or decrement the value of the binary code. The encoder logic is grouped so that the state of any single bit of the thermometer code can affect the state of one and only one bit of the binary code whereby when any least significant thermometer code bit is at an invalid logic level, the invalid level is propagated through the encoder circuit to only a single, least significant binary code bit, without the introduction of any logical errors. The invalid binary code bit is then stabilized to a valid level by one or more latches.
摘要翻译：编码器电路将温度计代码转换成等效的相邻二进制代码，其中只有一个位被改变以最小程度地增加或减少二进制代码的值。编码器逻辑被分组，使得温度计代码的任何单个位的状态可以影响二进制代码的一个且仅一个位的状态，由此当任何最不重要的温度计代码位处于无效逻辑电平时，无效级别通过编码器电路传播到仅一个最不重要的二进制码位，而不引入任何逻辑错误。然后，无效二进制码位由一个或多个锁存器稳定到有效电平。

47. 发明授权

US4613950A Self-calibrating time interval meter 失效
标题翻译：自校准时间间隔表
公开(公告)号：US4613950A
公开(公告)日：1986-09-23
申请号：US534854
申请日：1983-09-22
申请人： Daniel G. Knierim , Lee J. Jalovec
发明人： Daniel G. Knierim , Lee J. Jalovec
IPC分类号： G04F10/10 , G04F7/06
CPC分类号： G04F10/105
摘要： A self-calibrating time interval meter including means for measuring time intervals using a dual-speed ramp technique. The time interval meter operates in a measurement mode to measure time intervals and operates in a calibration mode for calibration adjustments. In measurement mode, the time interval meter utilizes a dual-speed ramp technique to expand the time interval to be measured. A capacitor is rapidly charged by a first constant current source during the time interval to be measured, and is then slowly discharged by a second constant current source. The time required to discharge the capacitor is measured and utilized to compute a measurement of the time interval. In calibration mode, a flip-flop is alternately switched into and out of the circuit to provide two time interval measurements that differ by exactly one clock period of a known clock signal. A microprocessor subtracts the two measurements and compares the difference to the known clock period to determine a calibration error. The microprocessor, through a digital-to-analog converter, varies the current flow of the first constant current source to minimize the calibration error by compensating for drift in the current sources.
摘要翻译：自校准时间间隔计，包括使用双速坡道技术测量时间间隔的装置。时间间隔计在测量模式下工作，以测量时间间隔，并在校准模式下进行校准调整。在测量模式下，时间间隔仪采用双速斜坡技术来扩展要测量的时间间隔。在测量的时间间隔期间，电容器由第一恒定电流源快速充电，然后由第二恒定电流源缓慢放电。测量放电电容器所需的时间并用于计算时间间隔的测量。在校准模式中，触发器被交替地切换到电路中并且从电路输出，以提供两个时间间隔测量值，该测量值与已知时钟信号的恰好一个时钟周期不同。微处理器减去两个测量值，并将差值与已知时钟周期进行比较，以确定校准误差。微处理器通过数模转换器改变第一恒流源的电流流动，通过补偿电流源中的漂移来最小化校准误差。

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