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41. 发明授权

US07453935B2 Multi-pair gigabit ethernet transceiver having decision feedback equalizer 有权
标题翻译：具有判决反馈均衡器的多对千兆以太网收发器
公开(公告)号：US07453935B2
公开(公告)日：2008-11-18
申请号：US11688669
申请日：2007-03-20
申请人： Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
发明人： Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/235 , H04B3/32 , H04L1/0021 , H04L1/0047 , H04L1/0053 , H04L1/0054 , H04L1/0059 , H04L1/006 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03197 , H04L25/03203 , H04L25/03235 , H04L25/03267 , H04L25/03987 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2001/0096 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.
摘要翻译：公开了为多对千兆位以太网收发器提供高速解码，增强的功率降低和时钟域划分的各种系统和方法。 ISI补偿分为两个阶段; 第一级补偿由解调器中的发射机的部分响应脉冲整形滤波器的特性引起的ISI分量，第二级补偿由维特比解码器中的多对传输信道的特性引起的ISI分量。基于从单位深度判决反馈均衡器接收的尾值和系数值的子集，通过从多个判决反馈均衡器向维特比提供输入信号来减小DFE深度来实现高速解码。通过自适应地截断NEXT，FEXT和回声消除滤波器中的有源抽头，或通过禁用解码器电路部分，如通道响应特性允许，实现功率降低。生成接收时钟信号，使得其与模拟采样时钟信号在频率上同步，并且相对于采样时钟信号之一具有特定的相位偏移。调整该相位偏移，使得由于来自数字部分到模拟部分的开关噪声的耦合而导致的系统性能降低被大大减小。

42. 发明授权

US07443910B2 PHY control module for a multi-pair gigabit transceiver 有权
标题翻译：用于多对千兆位收发器的PHY控制模块
公开(公告)号：US07443910B2
公开(公告)日：2008-10-28
申请号：US11175715
申请日：2005-07-06
申请人： Oscar E. Agazzi
发明人： Oscar E. Agazzi
IPC分类号： H04B1/38
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H03H21/0067 , H03H2021/007 , H03H2021/0074 , H04B3/23 , H04B3/32 , H04B3/487 , H04L1/0009 , H04L1/0054 , H04L1/08 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03267 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L69/323 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03681 , H04L2025/03745
摘要： A method for controlling operation of a multi-pair gigabit transceiver. The multi-pair gigabit transceiver comprises a Physical Layer Control module (PHY Control), a Physical Coding Sublayer module (PCS) and a Digital Signal Processing module (DSP). The PHY Control receives user-defined inputs from the Serial Management module and status signals from the DSP and the PCS and generates control signals, responsive to the user-defined inputs and the status signals, to the DSP and the PCS.
摘要翻译：一种用于控制多对千兆位收发器的操作的方法。多对千兆位收发器包括物理层控制模块（PHY Control），物理编码子层模块（PCS）和数字信号处理模块（DSP）。 PHY控制从串行管理模块接收用户定义的输入和来自DSP和PCS的状态信号，并根据用户定义的输入和状态信号生成控制信号到DSP和PCS。

43. 发明授权

US07305029B2 Multi-pair gigabit ethernet transceiver 有权
标题翻译：多对千兆以太网收发器
公开(公告)号：US07305029B2
公开(公告)日：2007-12-04
申请号：US10681624
申请日：2003-10-08
申请人： Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
发明人： Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/235 , H04B3/32 , H04L1/0021 , H04L1/0047 , H04L1/0053 , H04L1/0054 , H04L1/0059 , H04L1/006 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03197 , H04L25/03203 , H04L25/03235 , H04L25/03267 , H04L25/03987 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2001/0096 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.
摘要翻译：公开了为多对千兆位以太网收发器提供高速解码，增强的功率降低和时钟域划分的各种系统和方法。 ISI补偿分为两个阶段; 第一级补偿由解调器中的发射机的部分响应脉冲整形滤波器的特性引起的ISI分量，第二级补偿由维特比解码器中的多对传输信道的特性引起的ISI分量。基于从单位深度判决反馈均衡器接收的尾值和系数值的子集，通过从多个判决反馈均衡器向维特比提供输入信号来减小DFE深度来实现高速解码。通过自适应地截断NEXT，FEXT和回声消除滤波器中的有源抽头，或通过禁用解码器电路部分，如通道响应特性允许，实现功率降低。生成接收时钟信号，使得其与模拟采样时钟信号在频率上同步，并且相对于采样时钟信号之一具有特定的相位偏移。调整该相位偏移，使得由于来自数字部分到模拟部分的开关噪声的耦合而导致的系统性能降低被大大减小。

44. 发明授权

US07194029B2 Multi-pair gigabit ethernet transceiver having adaptive disabling or circuit elements 有权
标题翻译：具有自适应禁用或电路元件的多对千兆以太网收发器
公开(公告)号：US07194029B2
公开(公告)日：2007-03-20
申请号：US10681444
申请日：2003-10-08
申请人： Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
发明人： Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , David E. Kruse , Arthur Abnous , Henry Samueli
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/235 , H04B3/32 , H04L1/0021 , H04L1/0047 , H04L1/0053 , H04L1/0054 , H04L1/0059 , H04L1/006 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03197 , H04L25/03203 , H04L25/03235 , H04L25/03267 , H04L25/03987 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2001/0096 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.
摘要翻译：公开了为多对千兆位以太网收发器提供高速解码，增强的功率降低和时钟域划分的各种系统和方法。 ISI补偿分为两个阶段; 第一级补偿由解调器中的发射机的部分响应脉冲整形滤波器的特性引起的ISI分量，第二级补偿由维特比解码器中的多对传输信道的特性引起的ISI分量。基于从单位深度判决反馈均衡器接收的尾值和系数值的子集，通过从多个判决反馈均衡器向维特比提供输入信号来减小DFE深度来实现高速解码。通过自适应地截断NEXT，FEXT和回声消除滤波器中的有源抽头，或通过禁用解码器电路部分，如通道响应特性允许，实现功率降低。生成接收时钟信号，使得其与模拟采样时钟信号在频率上同步，并且相对于采样时钟信号之一具有特定的相位偏移。调整该相位偏移，使得由于来自数字部分到模拟部分的开关噪声的耦合而导致的系统性能降低被大大减小。

45. 发明授权

US06778602B2 Multi-pair gigabit ethernet transceiver 有权
标题翻译：多对千兆以太网收发器
公开(公告)号：US06778602B2
公开(公告)日：2004-08-17
申请号：US10086618
申请日：2002-02-28
申请人： Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , Henry Samueli , David E. Kruse , Arthur Abnous
发明人： Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , Henry Samueli , David E. Kruse , Arthur Abnous
IPC分类号： H03H730
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/235 , H04B3/32 , H04L1/0021 , H04L1/0047 , H04L1/0053 , H04L1/0054 , H04L1/0059 , H04L1/006 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03197 , H04L25/03203 , H04L25/03235 , H04L25/03267 , H04L25/03987 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2001/0096 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitters partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.
摘要翻译：公开了为多对千兆位以太网收发器提供高速解码，增强的功率降低和时钟域划分的各种系统和方法。 ISI补偿分为两个阶段; 第一级补偿由解调器中的发射机部分响应脉冲整形滤波器的特性引起的ISI分量，第二级补偿由维特比解码器中的多对传输信道的特性引起的ISI分量。基于从单位深度判决反馈均衡器接收的尾值和系数值的子集，通过从多个判决反馈均衡器向维特比提供输入信号来减小DFE深度来实现高速解码。通过自适应地截断NEXT，FEXT和回声消除滤波器中的有源抽头，或通过禁用解码器电路部分，如通道响应特性允许，实现功率降低。生成接收时钟信号，使得其与模拟采样时钟信号在频率上同步，并且相对于采样时钟信号之一具有特定的相位偏移。调整该相位偏移，使得由于来自数字部分到模拟部分的开关噪声的耦合而导致的系统性能降低被大大减小。

46. 发明授权

US06738419B2 Dynamic regulation of power consumption of a high-speed communication system 有权
公开(公告)号：US06738419B2
公开(公告)日：2004-05-18
申请号：US09952764
申请日：2001-09-10
申请人： Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , Henry Samueli
发明人： Oscar E. Agazzi , John L. Creigh , Mehdi Hatamian , Henry Samueli
IPC分类号： H03H730
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/32 , H04B3/487 , H04L1/0054 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03267 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： A method for dynamically regulating the power consumption of a high-speed integrated circuit which includes a multiplicity of processing blocks. A first metric and a second metric, which are respectively related to a first performance parameter and a second performance parameter of the integrated circuit, are defined. The first metric is set at a pre-defined value. Selected blocks of the multiplicity of processing blocks are disabled in accordance with a set of pre-determined patterns. The second metric is evaluated, while the disabling operation is being performed, to generate a range of values of the second metric. Each of the values corresponds to the pre-defined value of the first metric. A most desirable value of the second metric is determined from the range of values and is matched to a corresponding pre-determined pattern. The integrated circuit is subsequently operated with selected processing blocks disabled in accordance with the matching pre-determined pattern.

47. 发明授权

US06721916B2 System and method for trellis decoding in a multi-pair transceiver system 有权
标题翻译：用于多对收发器系统中网格解码的系统和方法
公开(公告)号：US06721916B2
公开(公告)日：2004-04-13
申请号：US09858990
申请日：2001-05-15
申请人： Oscar E. Agazzi , David Kruse , Arthur Abnous , Mehdi Hatamian
发明人： Oscar E. Agazzi , David Kruse , Arthur Abnous , Mehdi Hatamian
IPC分类号： H03M1303
CPC分类号： H04L7/0062 , G01R31/3004 , G01R31/3008 , G01R31/3016 , G01R31/31715 , G01R31/318502 , G01R31/318552 , G01R31/318594 , H04B3/23 , H04B3/32 , H04L1/0054 , H04L1/0059 , H04L1/242 , H04L7/0334 , H04L25/03038 , H04L25/03057 , H04L25/03146 , H04L25/03267 , H04L25/067 , H04L25/14 , H04L25/4917 , H04L25/497 , H04L2025/03363 , H04L2025/03369 , H04L2025/03477 , H04L2025/0349 , H04L2025/03496 , H04L2025/03503 , H04L2025/03617 , H04L2025/03745
摘要： A method and a system for decoding information signals encoded in accordance with a multi-state encoding scheme and transmitted over a multi-dimensional transmission channel by computing a distance of a received word from a codeword. One-dimensional (1D) input signals are processed in a pair of symbol decoders, implemented as look-up tables, to produce a pair of 1D errors, with each representing a distance metric between the input signal and a symbol in a set of symbols. The 1D errors are combined based on the multi-state encoding scheme in order to produce a set of multi-dimensional error terms. Each of the multi-dimensional error terms corresponds to a distance between a received word and a nearest codeword.
摘要翻译：一种用于对根据多状态编码方案编码并通过计算从码字的接收字的距离而在多维传输信道上传送的信息信号的方法和系统。一维（1D）输入信号在一对符号解码器中被处理，被实现为查找表，以产生一对1D误差，每一个代表一个输入信号和一组符号中的符号之间的距离度量。基于多状态编码方案组合1D误差，以产生一组多维误差项。多维误差项中的每一个对应于接收到的字和最近的码字之间的距离。

48. 发明授权

US06463041B1 Apparatus for, and method of, reducing noise in a communications system 有权
标题翻译：在通信系统中降低噪声的装置和方法
公开(公告)号：US06463041B1
公开(公告)日：2002-10-08
申请号：US09801235
申请日：2001-03-07
申请人： Oscar E. Agazzi
发明人： Oscar E. Agazzi
IPC分类号： H04B320
CPC分类号： H04B3/23 , H04B3/32 , H04B3/487
摘要： A communication line having a plurality of twisted wire pairs connects a plurality of transmitters, one transmitter at each end of each twisted wire pair, with a plurality of receivers, one receiver at each end of each twisted wire pair. Each receiver receives a combination signal including a direct signal from the transmitter at the opposite end of the twisted wire pair with which the receiver is associated and a plurality of far-end crosstalk (FEXT) impairment signals, one from each of the remaining transmitters at the opposite end of the communications line. A plurality of FEXT cancellation systems, one associated with each receiver, provides a replica FEXT impairment signal. A device associated with each receiver is responsive to the combination signal received by the receiver and the replica FEXT impairment signal provided by the FEXT cancellation system associated with the receiver for substantially removing the FEXT impairment signals from the combination signal. If necessary, a skew adjuster delays the arrival of the combination signal at the device so that the combination signal and the FEXT impairment signal arrive at the device at substantially the same time. A sequential decoder operates on signals from each of the plurality of wire pairs simultaneously to produce receiver outputs. A plurality of near-end crosstalk (NEXT) cancellation systems and echo cancellers remove NEXT and echo impairment signals from the combination signal.
摘要翻译：具有多条双绞线的通信线路连接多个发射器，每条双绞线对的每一端的一个发射器与多个接收器，每个双绞线对的每一端连接一个接收器。每个接收机接收组合信号，该组合信号包括来自发射机的直接信号，该信号位于与接收机相关联的双绞线对的相对端，以及多个远端串扰（FEXT）损伤信号，每个剩余发射机中的一个来自通信线路的另一端。与每个接收器相关联的多个FEXT取消系统提供复制FEXT损害信号。与每个接收机相关联的设备响应于由接收机接收的组合信号和由与接收机相关联的FEXT取消系统提供的副本FEXT损伤信号，以从组合信号基本上去除FEXT损害信号。如果需要，偏斜调整器将组合信号的到达延迟到设备，使得组合信号和FEXT损伤信号基本上同时到达设备。顺序解码器对来自多个线对中的每一个的信号同时操作以产生接收器输出。多个近端串扰（NEXT）消除系统和回波消除器从组合信号中去除NEXT和回波损害信号。

49. 发明授权

US5384806A Modem with time-invariant echo path 失效
标题翻译：调制解调器具有时间不变的回波路径
公开(公告)号：US5384806A
公开(公告)日：1995-01-24
申请号：US763800
申请日：1991-09-23
申请人： Oscar E. Agazzi
发明人： Oscar E. Agazzi
IPC分类号： H04B3/23 , H04L7/033 , H04Q11/04 , H04B1/38
CPC分类号： H04Q11/0471 , H04B3/23 , H04L7/0334 , H04L7/0331 , H04L7/0337 , H04Q2213/1319 , H04Q2213/13199 , H04Q2213/13202 , H04Q2213/13209 , H04Q2213/13214 , H04Q2213/1332 , H04Q2213/1336
摘要： An ISDN modem. The modem includes an independent clock which controls the modem's input and output filters and two dependent clocks whose rates are functions of the independent clock and which are synchronized with external timing signals. When a dependent clock is synchronized, timing adjustment signals to other components of the modem specify the type and direction of synchronization. One of the dependent clocks and the independent clock are used to control a decimator which provides two samples of a symbol which are one independent clock cycle apart. One of the samples is a primary sample from which the symbol is interpreted and the other is a secondary sample which is used to continually train a jitter canceller. When a clock is synchronized, the secondary sample becomes the primary sample, providing the modem with a time-invariant echo path. On clock synchronization, the jitter canceller responds to the timing adjustment signals by providing adaptation information to the linear echo canceller.
摘要翻译： ISDN调制解调器调制解调器包括一个独立的时钟，它控制调制解调器的输入和输出滤波器以及两个相关时钟，其速率是独立时钟的功能，并与外部定时信号同步。当从属时钟同步时，调制解调器的其他部件的定时调整信号指定同步的类型和方向。依赖时钟和独立时钟之一用于控制抽取器，该抽取器提供两个分开的独立时钟周期的符号样本。其中一个样本是符号被解释的主要样本，另一个是用于连续训练抖动消除器的次要样本。当时钟同步时，辅助样本成为主要样本，为调制解调器提供时间不变的回波路径。在时钟同步时，抖动消除器通过向线性回波消除器提供适配信息来响应定时调整信号。

50. 发明授权

US5353309A ISDN transmitter 失效
标题翻译： ISDN发射机
公开(公告)号：US5353309A
公开(公告)日：1994-10-04
申请号：US877902
申请日：1992-05-01
申请人： Oscar E. Agazzi , Steven R. Norsworthy
发明人： Oscar E. Agazzi , Steven R. Norsworthy
IPC分类号： H04L25/49 , H04B14/06
CPC分类号： H04L25/4919
摘要： A transmitter suitable for ISDN use feeds the 2B1Q transmit signals directly into a sigma-delta modulator. The input word is two or three bits and the datapath within the sigma-delta modulator need be only six bits wide. The sigma-delta modulator has sample-hold means which has some filtering effect. The additional filtering requirements are met with an analog filter. No digital interpolation filter is required.
摘要翻译：适用于ISDN使用的发射机将2B1Q发射信号直接馈入Σ-Δ调制器。输入字是两位或三位，并且Σ-Δ调制器内的数据路径只需要六位宽。 Σ-Δ调制器具有采样保持装置，具有一些滤波效果。模拟滤波器满足额外的滤波要求。不需要数字插值滤波器。

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