专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US07485515B2 Method of manufacturing metal oxide semiconductor 有权
标题翻译：制造金属氧化物半导体的方法
公开(公告)号：US07485515B2
公开(公告)日：2009-02-03
申请号：US11308641
申请日：2006-04-17
申请人： Neng-Kuo Chen , Teng-Chun Tsai , Chien-Chung Huang
发明人： Neng-Kuo Chen , Teng-Chun Tsai , Chien-Chung Huang
IPC分类号： H01L21/337
CPC分类号： H01L21/0217 , H01L21/0214 , H01L21/02167 , H01L21/02271 , H01L21/3145 , H01L21/3185 , H01L21/823807 , H01L29/7843 , H01L29/7845
摘要： A method of forming compressive nitride film is provided. The method includes performing a chemical vapor deposition (CVD) process to form a nitride film on a substrate, and the method is characterized by adding a certain gas, selected from among Ar, N2, Kr, Xe, and mixtures thereof. Due to the addition of the foregoing certain gas, it can increase the compressive stress, thereby increasing PMOS drive current gain.
摘要翻译：提供一种形成压缩氮化物膜的方法。该方法包括进行化学气相沉积（CVD）工艺以在衬底上形成氮化物膜，该方法的特征在于加入选自Ar，N2，Kr，Xe及其混合物中的某些气体。由于加入上述某些气体，可以增加压缩应力，从而增加PMOS驱动电流增益。

42. 发明申请

US20080237748A1 METHOD FOR FABRICATING HIGH COMPRESSIVE STRESS FILM AND STRAINED-SILICON TRANSISTORS 审中-公开
公开(公告)号：US20080237748A1
公开(公告)日：2008-10-02
申请号：US12123452
申请日：2008-05-19
申请人： Neng-Kuo Chen , Teng-Chun Tsai , Chien-Chung Huang
发明人： Neng-Kuo Chen , Teng-Chun Tsai , Chien-Chung Huang
IPC分类号： H01L29/00
CPC分类号： H01L21/31633 , H01L21/02126 , H01L21/02211 , H01L21/02274 , H01L21/823807 , H01L23/3192 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating strained silicon transistors is disclosed. First, a semiconductor substrate is provided, in which the semiconductor substrate includes a gate, at least a spacer, and a source/drain region formed thereon. Next, a precursor, silane, and ammonia are injected, in which the precursor is reacted with silane and ammonia to form a high compressive stress film on the surface of the gate, the spacer, and the source/drain region. Preferably, the high compressive stress film can be utilized in the fabrication of a poly stressor, a contact etch stop layer, and dual contact etch stop layers.

43. 发明申请

US20080188091A1 SEMICONDUCTOR DEVICE, METHOD FOR FABRICATING THEREOF AND METHOD FOR INCREASING FILM STRESS 审中-公开
标题翻译：半导体器件，其制造方法和增加膜应力的方法
公开(公告)号：US20080188091A1
公开(公告)日：2008-08-07
申请号：US12043905
申请日：2008-03-06
申请人： SHAO-TA HSU , Teng-Chun Tsai , Neng-Kuo Chen , Hsiu-Lien Liao , Cheng-Han Wu , Wen-Han Hung
发明人： SHAO-TA HSU , Teng-Chun Tsai , Neng-Kuo Chen , Hsiu-Lien Liao , Cheng-Han Wu , Wen-Han Hung
IPC分类号： H01L21/469
CPC分类号： H01L27/092 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76829 , H01L21/823807 , H01L29/7843
摘要： A method for forming a semiconductor device is provided. The method comprises steps of providing a substrate having a first-conductive-type transistor and a second-conductive-type transistor formed thereon and then forming a stress layer over the substrate to conformally cover the first-conductive-type transistor and the second-conductive-type transistor. A cap layer is formed on the stress layer over the first-conductive-type transistor. A modification process is performed. The cap layer is removed.
摘要翻译：提供一种形成半导体器件的方法。该方法包括以下步骤：提供具有形成在其上的第一导电型晶体管和第二导电型晶体管的衬底，然后在衬底上形成应力层以共形覆盖第一导电型晶体管和第二导电型晶体管型晶体管。在第一导电型晶体管上的应力层上形成覆盖层。执行修改处理。盖层被去除。

44. 发明申请

US20070264836A1 Method for forming a gate and etching a conductive layer 有权
标题翻译：形成栅极并蚀刻导电层的方法
公开(公告)号：US20070264836A1
公开(公告)日：2007-11-15
申请号：US11382470
申请日：2006-05-09
申请人： Neng-Kuo Chen , Teng-Chun Tsai , Hsiu-Lien Liao
发明人： Neng-Kuo Chen , Teng-Chun Tsai , Hsiu-Lien Liao
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/32139 , H01L21/28035 , H01L21/28202 , H01L21/31111 , H01L29/518
摘要： A method for forming a gate and a method for etching a conductive layer are provided. First, a substrate is provided, including a dielectric layer and a conductive layer on its surface in order. Subsequently, a patterned silicon nitride layer is formed on the conductive layer as a hard mask, and the hydrogen concentration of the patterned silicon nitride layer is more than 1022 atoms/cm3. Thereafter, the conductive layer and the dielectric layer are etched utilizing the hard mask as a mask. Finally, an etching solution is utilized to remove the hard mask.
摘要翻译：提供一种形成栅极的方法和蚀刻导电层的方法。首先，在其表面上依次提供包括电介质层和导电层的基板。随后，在导电层上形成图案化氮化硅层作为硬掩模，并且图案化氮化硅层的氢浓度大于10 22原子/ cm 3 >。此后，使用硬掩模作为掩模蚀刻导电层和电介质层。最后，使用蚀刻溶液去除硬掩模。

45. 发明申请

US20070117370A1 METHOD OF FORMING CONTACT AND SEMICONDUCTOR DEVICE 有权
标题翻译：形成接触和半导体器件的方法
公开(公告)号：US20070117370A1
公开(公告)日：2007-05-24
申请号：US11164481
申请日：2005-11-24
申请人： Neng-Kuo Chen , Teng-Chun Tsai , Chien-Chung Huang
发明人： Neng-Kuo Chen , Teng-Chun Tsai , Chien-Chung Huang
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L21/76837 , H01L21/76801
摘要： A method of forming a contact is provided. A substrate having at least two metal oxide semiconductor devices is provided and a gap is formed between the two devices. A first stress layer is formed over the substrate to cover the metal-oxide semiconductor devices and the substrate. The first stress layer is formed by first forming a first stress material layer over the substrate to cover the metal-oxide semiconductor devices and to fill the gap, wherein the stress material inside the gap has a seam. An etching back process is then performed to remove a portion of the stress material layer inside the gap. A second stress layer and a dielectric layer are sequentially formed on the first stress layer. A portion of the second stress layer is removed to form a contact opening. A second conductive layer is filled into the contact opening to form a contact.
摘要翻译：提供了形成接触的方法。提供具有至少两个金属氧化物半导体器件的衬底，并且在两个器件之间形成间隙。在衬底上形成第一应力层以覆盖金属氧化物半导体器件和衬底。第一应力层通过首先在衬底上形成第一应力材料层以覆盖金属氧化物半导体器件并填充间隙而形成，其中间隙内的应力材料具有接缝。然后执行回蚀处理以去除间隙内部的应力材料层的一部分。第一应力层和电介质层依次形成在第一应力层上。去除第二应力层的一部分以形成接触开口。将第二导电层填充到接触开口中以形成接触。

46. 发明申请

US20070105292A1 Method for fabricating high tensile stress film and strained-silicon transistors 审中-公开
标题翻译：制造高拉伸应力膜和应变硅晶体管的方法
公开(公告)号：US20070105292A1
公开(公告)日：2007-05-10
申请号：US11163988
申请日：2005-11-07
申请人： Neng-Kuo Chen , Teng-Chun Tsai , Hsiu-Lien Liao , Chien-Chung Huang
发明人： Neng-Kuo Chen , Teng-Chun Tsai , Hsiu-Lien Liao , Chien-Chung Huang
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L21/324 , H01L21/7624 , H01L29/6656 , H01L29/78 , H01L29/7843
摘要： A method for fabricating high tensile stress film and strained-silicon transistors. First, a semiconductor substrate is provided and a gate, at least a spacer, and a source/drain region are formed on the semiconductor substrate. Next, n deposition processes are performed to form n layers of high tensile stress film over the surface of the gate and the source/drain region, in which each high tensile stress film is treated with a heat treatment process and n is greater than or equal to two.
摘要翻译：一种制造高拉伸应力膜和应变硅晶体管的方法。首先，提供半导体衬底，并且在半导体衬底上形成栅极，至少间隔物和源极/漏极区。接下来，进行n个沉积工艺以在栅极和源极/漏极区域的表面上形成n层高拉伸应力膜，其中每个高拉伸应力膜用热处理工艺处理，并且n大于或等于到两个。

47. 发明申请

US20070020875A1 SEAMLESS TRENCH FILL METHOD UTILIZING SUB-ATMOSPHERIC PRESSURE CHEMICAL VAPOR DEPOSITION TECHNIQUE 有权
标题翻译：使用亚大气压化学气相沉积技术的无缝渗透膜方法
公开(公告)号：US20070020875A1
公开(公告)日：2007-01-25
申请号：US11161074
申请日：2005-07-21
申请人： Shao-Ta Hsu , Neng-Kuo Chen , Teng-Chun Tsai
发明人： Shao-Ta Hsu , Neng-Kuo Chen , Teng-Chun Tsai
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： A seamless trench fill method utilizing ozone-assisted sub-atmospheric pressure chemical vapor deposition (SACVD) technique is provided. After the deposition of a SACVD silicon oxide film, the substrate is subjected to a steam anneal that is performed under H2O2 environment at a relatively lower temperature ranging between 500° C. and 800° C. for a time period of no less than 30 minutes. The seam defect in the trench is effectively eliminated by this low-temperature steam anneal. To densify the SACVD silicon oxide film, a subsequent N2 anneal is carried out at a higher temperature, for example, 1050° C.
摘要翻译：提供了利用臭氧辅助亚大气压化学气相沉积（SACVD）技术的无缝沟槽填充方法。在沉积SACVD氧化硅膜之后，将衬底经受在H 2 O 2 O 2环境下进行的蒸汽退火，温度在500° C.和800℃，时间不少于30分钟。通过这种低温蒸汽退火有效地消除了沟槽中的接缝缺陷。为了致密化SACVD氧化硅膜，随后的N 2 H 3退火在更高的温度例如1050℃下进行。

48. 发明授权

US09263252B2 Method of protecting an interlayer dielectric layer and structure formed thereby 有权
标题翻译：保护层间电介质层的方法和由此形成的结构
公开(公告)号：US09263252B2
公开(公告)日：2016-02-16
申请号：US13735949
申请日：2013-01-07
申请人： Chun-Wei Chang , Yi-An Lin , Neng-Kuo Chen , Sey-Ping Sun , Clement Hsingjen Wann , Yu-Lien Huang
发明人： Chun-Wei Chang , Yi-An Lin , Neng-Kuo Chen , Sey-Ping Sun , Clement Hsingjen Wann , Yu-Lien Huang
IPC分类号： H01L29/78 , H01L21/336 , H01L21/02 , H01L29/66
CPC分类号： H01L21/022 , H01L29/66545
摘要： This description relates to a method including forming an interlayer dielectric (ILD) layer and a dummy gate structure over a substrate and forming a cavity in a top portion of the ILD layer. The method further includes forming a protective layer to fill the cavity. The method further includes planarizing the protective layer. A top surface of the planarized protective layer is level with a top surface of the dummy gate structure. This description also relates to a semiconductor device including first and second gate structures and an ILD layer formed on a substrate. The semiconductor device further includes a protective layer formed on the ILD layer, the protective layer having a different etch selectivity than the ILD layer, where a top surface of the protective layer is level with the top surfaces of the first and second gate structures.
摘要翻译：该描述涉及包括在衬底上形成层间电介质（ILD）层和虚拟栅极结构并在ILD层的顶部形成腔的方法。该方法还包括形成保护层以填充空腔。该方法还包括平坦化保护层。平坦化保护层的顶表面与虚拟栅结构的顶表面平齐。该描述还涉及包括第一和第二栅极结构以及形成在衬底上的ILD层的半导体器件。半导体器件还包括形成在ILD层上的保护层，保护层具有与ILD层不同的蚀刻选择性，其中保护层的顶表面与第一和第二栅极结构的顶表面平齐。

49. 发明授权

US09006802B2 Semiconductor device manufacturing methods and methods of forming insulating material layers 有权
标题翻译：形成绝缘材料层的半导体器件制造方法和方法
公开(公告)号：US09006802B2
公开(公告)日：2015-04-14
申请号：US13212834
申请日：2011-08-18
申请人： Gin-Chen Huang , Tsai-Fu Hsiao , Ching-Hong Jiang , Neng-Kuo Chen , Hongfa Luan , Sey-Ping Sun , Clement Hsingjen Wann
发明人： Gin-Chen Huang , Tsai-Fu Hsiao , Ching-Hong Jiang , Neng-Kuo Chen , Hongfa Luan , Sey-Ping Sun , Clement Hsingjen Wann
IPC分类号： H01L29/78 , H01L21/02 , H01L29/66
CPC分类号： H01L21/02274 , H01L21/02164 , H01L21/022 , H01L21/0228 , H01L21/02332 , H01L21/324 , H01L29/66795
摘要： Semiconductor device manufacturing methods and methods of forming insulating material layers are disclosed. In one embodiment, a method of forming a composite insulating material layer of a semiconductor device includes providing a workpiece and forming a first sub-layer of the insulating material layer over the workpiece using a first plasma power level. A second sub-layer of the insulating material layer is formed over the first sub-layer of the insulating material layer using a second plasma power level, and the workpiece is annealed.
摘要翻译：公开了形成绝缘材料层的半导体器件制造方法和方法。在一个实施例中，形成半导体器件的复合绝缘材料层的方法包括提供工件并使用第一等离子体功率电平在工件上形成绝缘材料层的第一子层。使用第二等离子体功率电平在绝缘材料层的第一子层上形成绝缘材料层的第二子层，并且将工件退火。

50. 发明授权

US08344343B2 Composite film for phase change memory devices 有权
标题翻译：用于相变存储器件的复合膜
公开(公告)号：US08344343B2
公开(公告)日：2013-01-01
申请号：US12750323
申请日：2010-03-30
申请人： Tung-Ti Yeh , Neng-Kuo Chen , Cheng-Yuan Tsai , Chung-Yi Yu , Chia-Shiung Tsai
发明人： Tung-Ti Yeh , Neng-Kuo Chen , Cheng-Yuan Tsai , Chung-Yi Yu , Chia-Shiung Tsai
IPC分类号： H01L29/04 , H01L29/02 , H01L47/00 , H01L21/06
CPC分类号： H01L45/1226 , H01L45/06 , H01L45/144 , H01L45/1675
摘要： A phase change memory device and a method of manufacture are provided. The phase change memory device includes a phase change layer electrically coupled to a top electrode and a bottom electrode, the phase change layer comprising a phase change material. A mask layer is formed overlying the phase change layer. A first sealing layer is formed overlying the mask layer, and a second sealing layer is formed overlying the first sealing layer.
摘要翻译：提供了一种相变存储器件及其制造方法。相变存储器件包括电耦合到顶电极和底电极的相变层，所述相变层包括相变材料。掩模层形成在相变层上。形成覆盖在掩模层上的第一密封层，并且形成覆盖在第一密封层上的第二密封层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式