专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US5210601A Compression contacted semiconductor device and method for making of the same 失效
标题翻译：压接式半导体器件及其制造方法
公开(公告)号：US5210601A
公开(公告)日：1993-05-11
申请号：US817952
申请日：1992-01-06
申请人： Mitsuhiko Kitagawa , Yoshio Yokota , Kazuo Watanuki, deceased
发明人： Mitsuhiko Kitagawa , Yoshio Yokota , Kazuo Watanuki, deceased
IPC分类号： H01L23/48
CPC分类号： H01L24/72 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01074 , H01L2924/10253 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055
摘要： According to this invention, a compression contacted semiconductor device is characterized by including a semiconductor pellet having main electrodes formed a first major surface of one surface side and a second major surface of another surface side, and electrode posts arranged on at least one major surface of the semiconductor pellet through an electrode member to sandwich the semiconductor pellet to compress the electrodes of the first and second major surfaces, wherein a crystal defect density is distributed within a surface of the semiconductor pellet so that a carrier lifetime of at least heat generating portions in the surface of the semiconductor pellet which do not sufficiently conduct heat to the electrode posts is shorter than a carrier lifetime of major heat generating portions which sufficiently conduct heat to the electrode posts. For this reason, current in the heat generating portions which do not sufficiently conduct heat to the electrode members is decreased. Therefore, the amount of heat generation is reduced, and the break-down voltage of a semiconductor element is increased.
摘要翻译：根据本发明，压电接触半导体器件的特征在于包括：半导体芯片，其具有形成有一个表面侧的第一主表面和另一个表面侧的第二主表面的主电极，以及设置在至少一个主表面上的电极柱所述半导体颗粒通过电极构件夹持半导体颗粒以压缩第一和第二主表面的电极，其中晶体缺陷密度分布在半导体芯片的表面内，使得至少发热部分的载流子寿命不足够地向电极柱传导热量的半导体芯片的表面比向电极柱充分传导热量的主要发热部分的载流子寿命短。因此，不能充分地向电极部件传导热量的发热部的电流降低。因此，发热量减少，半导体元件的击穿电压升高。

42. 发明授权

US09001382B2 Image forming system and image forming apparatus configured for cost priority mode processing 有权
标题翻译：图像形成系统和图像形成装置被配置用于成本优先模式处理
公开(公告)号：US09001382B2
公开(公告)日：2015-04-07
申请号：US13357041
申请日：2012-01-24
申请人： Mitsuhiko Kitagawa
发明人： Mitsuhiko Kitagawa
IPC分类号： H04N1/60 , H04N1/00 , H04N1/203 , H04N1/23 , H04N1/29 , H04N1/333
CPC分类号： H04N1/60 , G03G15/50 , H04N1/00204 , H04N1/00278 , H04N1/2032 , H04N1/2338 , H04N1/2369 , H04N1/295 , H04N1/33315 , H04N1/33369
摘要： An image forming system includes an image forming apparatus and an upper device connected to the image forming apparatus. The image forming apparatus includes a first receiving unit for receiving a print mode including a cost priority mode; a first transmission unit for transmitting the print mode to the upper device; a second receiving unit for receiving a print instruction; a print control unit for printing the print data; a duplex print control unit for controlling a printing operation; and a fixing temperature control unit for controlling a fixing temperature. The upper device includes a first storage unit for storing a save setting; a third receiving unit for receiving image data; a second storage unit for storing the print mode; an arrangement print control unit for generating the print data; and a second transmission unit for transmitting the print instruction.
摘要翻译：图像形成系统包括图像形成装置和连接到图像形成装置的上部装置。图像形成装置包括：第一接收单元，用于接收包括成本优先模式的打印模式; 第一发送单元，用于将打印模式发送到上位装置; 用于接收打印指令的第二接收单元; 用于打印打印数据的打印控制单元; 用于控制打印操作的双面打印控制单元; 以及用于控制定影温度的定影温度控制单元。上部装置包括用于存储保存设置的第一存储单元; 用于接收图像数据的第三接收单元; 用于存储打印模式的第二存储单元; 布置打印控制单元，用于生成打印数据; 以及用于发送打印指令的第二传送单元。

43. 发明授权

US08581298B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08581298B2
公开(公告)日：2013-11-12
申请号：US12724243
申请日：2010-03-15
申请人： Mitsuhiko Kitagawa
发明人： Mitsuhiko Kitagawa
IPC分类号： H01L29/74
CPC分类号： H01L27/088 , H01L29/0634 , H01L29/0856 , H01L29/0878 , H01L29/4236 , H01L29/7391 , H01L29/7394 , H01L29/7397 , H01L29/7813 , H01L29/7824 , H01L29/7825 , H01L29/7828 , H01L29/7831 , H01L29/7838
摘要： A semiconductor device includes: a semiconductor layer having a first end portion and a second end portion; a first main electrode provided on the first end portion and electrically connected to the semiconductor layer; a second main electrode provided on the second end portion and electrically connected to the semiconductor layer; a first gate electrode provided via a first gate insulating film in a plurality of first trenches formed from the first end portion toward the second end portion; and a second gate electrode provided via a second gate insulating film in a plurality of second trenches formed from the second end portion toward the first end portion. Spacing between a plurality of the first gate electrodes and spacing between a plurality of the second gate electrodes are 200 nm or less.
摘要翻译：半导体器件包括：具有第一端部和第二端部的半导体层; 第一主电极，设置在第一端部上并与半导体层电连接; 第二主电极，设置在第二端部并与半导体层电连接; 第一栅电极，其经由第一栅极绝缘膜设置在由所述第一端部朝向所述第二端部形成的多个第一沟槽中; 以及第二栅电极，其经由第二栅极绝缘膜设置在由所述第二端部朝向所述第一端部形成的多个第二沟槽中。多个第一栅电极之间的间隔和多个第二栅电极之间的间隔为200nm以下。

44. 发明申请

US20120043638A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20120043638A1
公开(公告)日：2012-02-23
申请号：US13287562
申请日：2011-11-02
申请人： Mitsuhiko Kitagawa
发明人： Mitsuhiko Kitagawa
IPC分类号： H01L29/06
CPC分类号： H01L29/861 , H01L21/84 , H01L29/0692 , H01L29/0696 , H01L29/405 , H01L29/407 , H01L29/7394 , H01L29/7824 , H01L29/785 , H01L29/8611 , H01L33/34
摘要： A semiconductor device includes: a first insulating layer; a semiconductor layer provided on the first insulating layer; a first semiconductor region selectively provided in the semiconductor layer; a second semiconductor region selectively provided in the semiconductor layer and spaced from the first semiconductor region; a first main electrode provided in contact with the first semiconductor region; a second main electrode provided in contact with the second semiconductor region; a second insulating layer provided on the semiconductor layer; a first conductive material provided in the second insulating layer above a portion of the semiconductor layer located between the first semiconductor region and the second semiconductor region; and a second conductive material provided in a trench provided in a portion of the semiconductor layer opposed to the first conductive material, being in contact with the first conductive material, and reaching the first insulating layer.
摘要翻译：一种半导体器件包括：第一绝缘层; 设置在所述第一绝缘层上的半导体层; 选择性地设置在所述半导体层中的第一半导体区域; 选择性地设置在所述半导体层中并与所述第一半导体区隔开的第二半导体区域; 设置成与所述第一半导体区域接触的第一主电极; 设置成与第二半导体区域接触的第二主电极; 设置在所述半导体层上的第二绝缘层; 设置在位于所述第一半导体区域和所述第二半导体区域之间的所述半导体层的部分上方的所述第二绝缘层中的第一导电材料; 以及设置在与所述第一导电材料相对的所述半导体层的与所述第一导电材料相接触并且到达所述第一绝缘层的部分中的沟槽中的第二导电材料。

45. 发明授权

US07498635B2 Field effect transistor and application device thereof 失效
标题翻译：场效应晶体管及其应用器件
公开(公告)号：US07498635B2
公开(公告)日：2009-03-03
申请号：US11249894
申请日：2005-10-12
申请人： Mitsuhiko Kitagawa , Yoshiaki Aizawa
发明人： Mitsuhiko Kitagawa , Yoshiaki Aizawa
IPC分类号： H01L29/76
CPC分类号： H01L29/7801 , H01L25/167 , H01L29/0634 , H01L29/0696 , H01L29/1045 , H01L29/4232 , H01L29/42356 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/78 , H01L29/7813 , H01L29/7816 , H01L29/7824 , H01L29/7825 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a MOSFET having a low on-state resistance and a high withstand voltage as well as a small output capacitance (C(gd), etc.). The MOSFET has a p-type base layer 4 and a n-type source layer 5 selectively formed on the surface of the p-type base layer 4. A n-type drain layer 7 is formed in a position apart from the p-type base layer 4. On the surface of the region between the p-type base layer 4 and the n-type drain layer 7, a n-type drift semiconductor layer 12 and a p-type drift semiconductor layer 13 are alternately arranged from the p-type base layer 4 to the n-type drain layer 7. Further, in the region between the n-type source layer 5 and the n-type drain layer 7, a gate electrode 15 is formed via a gate insulating film 14. With the structure, the neighboring region of the gate electrode is depleted by a built in potential between the n-type drift semiconductor layer 12 and the p-type drift semiconductor layer 13 or by the potential of the gate electrode, when the gate electrode, source electrode, and drain electrode are at 0 potential.
摘要翻译：本发明提供具有低导通电阻和高耐受电压以及小的输出电容（C（gd）等）的MOSFET。 MOSFET具有选择性地形成在p型基极层4的表面上的p型基极层4和n型源极层5.n型漏极层7形成在与p型基极层4隔开的位置在p型基极层4和n型漏极层7之间的区域的表面上，n型漂移半导体层12和p型漂移半导体层13从p 类型的基极层4到n型漏极层7.此外，在n型源极层5和n型漏极层7之间的区域中，通过栅极绝缘膜14形成栅极15。当n型漂移半导体层12和p型漂移半导体层13之间的栅电极的相邻区域被栅极电极的内部电位耗尽时，栅电极的相邻区域耗尽栅电极的电位电极和漏电极为0电位。

46. 发明授权

US07202526B2 Field effect transistor and application device thereof 有权
标题翻译：场效应晶体管及其应用器件
公开(公告)号：US07202526B2
公开(公告)日：2007-04-10
申请号：US10864098
申请日：2004-06-09
申请人： Mitsuhiko Kitagawa , Yoshiaki Aizawa
发明人： Mitsuhiko Kitagawa , Yoshiaki Aizawa
IPC分类号： H01L29/76
CPC分类号： H01L29/7801 , H01L25/167 , H01L29/0634 , H01L29/0696 , H01L29/1045 , H01L29/4232 , H01L29/42356 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/78 , H01L29/7813 , H01L29/7816 , H01L29/7824 , H01L29/7825 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a MOSFET having a low on-state resistance and a high withstand voltage as well as a small output capacitance (C(gd), etc.). The MOSFET has a p-type base layer 4 and a n-type source layer 5 selectively formed on the surface of the p-type base layer. 4. A n-type drain layer 7 is formed in a position apart from the p-type base layer 4. On the surface of the region between the p-type base layer 4 and the n-type drain layer 7, a n-type drift semiconductor layer 12 and a p-type drift semiconductor layer 13 are alternately arranged from the p-type base layer 4 to the n-type drain layer 7. Further, in the region between the n-type source layer 5 and the n-type drain layer 7, a gate electrode 15 is formed via a gate insulating film 14. With the structure, the neighboring region of the gate electrode is depleted by a built in potential between the n-type drift semiconductor layer 12 and the p-type drift semiconductor layer 13 or by the potential of the gate electrode, when the gate electrode, source electrode, and drain electrode are at 0 potential.
摘要翻译：本发明提供具有低导通电阻和高耐受电压以及小的输出电容（C（gd）等）的MOSFET。 MOSFET具有选择性地形成在p型基极层的表面上的p型基极层4和n型源极层5。 4。 n型漏极层7形成在离开p型基极层4的位置。在p型基极层4和n型漏极层7之间的区域的表面上，n型漂移半导体层12和p型漂移半导体层13从p型基极层 4到n型漏极层7。此外，在n型源极层5和n型漏极层7之间的区域中，通过栅极绝缘膜14形成栅电极15。利用该结构，栅电极的相邻区域在n型漂移半导体层12和p型漂移半导体层13之间的内置电位或栅电极的电位耗尽，源电极和漏电极为0电位。

47. 发明申请

US20070023831A1 Field Effect Transistor and Application Device Thereof 有权
标题翻译：场效应晶体管及其应用器件
公开(公告)号：US20070023831A1
公开(公告)日：2007-02-01
申请号：US11462634
申请日：2006-08-04
申请人： Mitsuhiko Kitagawa , Yoshiaki Aizawa
发明人： Mitsuhiko Kitagawa , Yoshiaki Aizawa
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/7801 , H01L25/167 , H01L29/0634 , H01L29/0696 , H01L29/1045 , H01L29/4232 , H01L29/42356 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/78 , H01L29/7813 , H01L29/7816 , H01L29/7824 , H01L29/7825 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a MOSFET having a low on-state resistance and a high withstand voltage as well as a small output capacitance (C(gd), etc.). The MOSFET has a p-type base layer 4 and a n-type source layer 5 selectively formed on the surface of the p-type base layer 4. A n-type drain layer 7 is formed in a position apart from the p-type base layer 4. On the surface of the region between the p-type base layer 4 and the n-type drain layer 7, a n-type drift semiconductor layer 12 and a p-type drift semiconductor layer 13 are alternately arranged from the p-type base layer 4 to the n-type drain layer 7. Further, in the region between the n-type source layer 5 and the n-type drain layer 7, a gate electrode 15 is formed via a gate insulating film 14. With the structure, the neighboring region of the gate electrode is depleted by a built in potential between the n-type drift semiconductor layer 12 and the p-type drift semiconductor layer 13 or by the potential of the gate electrode, when the gate electrode, source electrode, and drain electrode are at 0 potential.
摘要翻译：本发明提供具有低导通电阻和高耐受电压以及小的输出电容（C（gd）等）的MOSFET。 MOSFET具有选择性地形成在p型基极层4的表面上的p型基极层4和n型源极层5.n型漏极层7形成在与p型基极层4隔开的位置在p型基极层4和n型漏极层7之间的区域的表面上，n型漂移半导体层12和p型漂移半导体层13从p 类型的基极层4到n型漏极层7.此外，在n型源极层5和n型漏极层7之间的区域中，通过栅极绝缘膜14形成栅极15。当n型漂移半导体层12和p型漂移半导体层13之间的栅电极的相邻区域被栅极电极的内部电位耗尽时，栅电极的相邻区域耗尽栅电极的电位电极和漏电极为0电位。

48. 发明申请

US20060033157A1 Field effect transistor and application device thereof 失效
公开(公告)号：US20060033157A1
公开(公告)日：2006-02-16
申请号：US11249894
申请日：2005-10-12
申请人： Mitsuhiko Kitagawa , Yoshiaki Aizawa
发明人： Mitsuhiko Kitagawa , Yoshiaki Aizawa
IPC分类号： H01L29/76 , H01L27/12
CPC分类号： H01L29/7801 , H01L25/167 , H01L29/0634 , H01L29/0696 , H01L29/1045 , H01L29/4232 , H01L29/42356 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/78 , H01L29/7813 , H01L29/7816 , H01L29/7824 , H01L29/7825 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a MOSFET having a low on-state resistance and a high withstand voltage as well as a small output capacitance (C(gd), etc.). The MOSFET has a p-type base layer 4 and a n-type source layer 5 selectively formed on the surface of the p-type base layer 4. A n-type drain layer 7 is formed in a position apart from the p-type base layer 4. On the surface of the region between the p-type base layer 4 and the n-type drain layer 7, a n-type drift semiconductor layer 12 and a p-type drift semiconductor layer 13 are alternately arranged from the p-type base layer 4 to the n-type drain layer 7. Further, in the region between the n-type source layer 5 and the n-type drain layer 7, a gate electrode 15 is formed via a gate insulating film 14. With the structure, the neighboring region of the gate electrode is depleted by a built in potential between the n-type drift semiconductor layer 12 and the p-type drift semiconductor layer 13 or by the potential of the gate electrode, when the gate electrode, source electrode, and drain electrode are at 0 potential.

49. 发明申请

US20050253190A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20050253190A1
公开(公告)日：2005-11-17
申请号：US11101570
申请日：2005-04-08
申请人： Hideki Okumura , Mitsuhiko Kitagawa , Takuma Hara , Takayoshi Ino , Kiyotaka Arai , Satoshi Taji , Masanobu Tsuchitani
发明人： Hideki Okumura , Mitsuhiko Kitagawa , Takuma Hara , Takayoshi Ino , Kiyotaka Arai , Satoshi Taji , Masanobu Tsuchitani
IPC分类号： H01L29/78 , H01L27/04 , H01L29/06 , H01L29/10 , H01L29/423 , H01L29/94
CPC分类号： H01L29/7813 , H01L29/0653 , H01L29/1095 , H01L29/42368
摘要： A semiconductor device comprises a semiconductor substrate; a semiconductor layer provided on the surface of the semiconductor substrate; a base layer provided on the surface of the semiconductor layer; a source layer provided on the surface of the base layer; a trench formed to pass through the source layer, the base layer, and the semiconductor layer from the surface of the source layer, and reaching the semiconductor substrate; a gate electrode provided from the source layer to at least the semiconductor layer within the trench; and an insulator provided between the gate electrode and the base layer so as to fill in the inside of the trench below the gate electrode, the insulator insulating the gate electrode from the base layer, and generating a potential distribution from the gate electrode toward the semiconductor substrate when a voltage is applied to the gate electrode.
摘要翻译：半导体器件包括半导体衬底; 设置在所述半导体衬底的表面上的半导体层; 设置在所述半导体层的表面上的基底层; 源层，设置在基层的表面上; 形成为从源极层的表面通过源极层，基极层和半导体层并到达半导体基板的沟槽; 从所述源极层至所述沟槽内的所述半导体层设置的栅电极; 以及设置在所述栅电极和所述基极层之间的绝缘体，以便填充所述栅电极下方的所述沟槽的内部，所述绝缘体将所述栅电极与所述基极层绝缘，并且从所述栅电极向所述半导体产生电势分布衬底，当电压施加到栅电极时。

50. 发明授权

US5796125A High breakdown voltage semiconductor device using trench grooves 失效
标题翻译：高耐压半导体器件采用沟槽
公开(公告)号：US5796125A
公开(公告)日：1998-08-18
申请号：US528570
申请日：1995-09-15
申请人： Tomoko Matsudai , Mitsuhiko Kitagawa , Akio Nakagawa
发明人： Tomoko Matsudai , Mitsuhiko Kitagawa , Akio Nakagawa
IPC分类号： H01L29/06 , H01L29/423 , H01L29/739 , H01L29/78 , H01L29/74 , H01L29/76 , H01L29/94 , H01L31/111
CPC分类号： H01L29/0696 , H01L29/7394 , H01L29/7398 , H01L29/7809 , H01L29/7824 , H01L29/4238
摘要： A high breakdown voltage semiconductor device. The device includes a semiconductor substrate, an insulating film formed on the semiconductor substrate, an active region formed on the insulating film, drain and base regions formed in a surface portion of the active region, and a source region formed in a surface portion of the base region. First and second gate insulating films are formed on inner surfaces of first and second grooves penetrating the base region so as to come in contact with the source region and reaching the active region, with first and second electrodes being buried in the first and second grooves. Two or more channel regions are formed in a MOS structure constructed by the gate insulating film, the gate electrode, the source region, the base region and the active region.
摘要翻译：高耐压半导体器件。该器件包括半导体衬底，形成在半导体衬底上的绝缘膜，形成在绝缘膜上的有源区，形成在有源区的表面部分中的漏极和基极区以及形成在有源区的表面部分中的源极区基地区。第一和第二栅极绝缘膜形成在穿过基极区域的第一和第二沟槽的内表面上，以便与源极区域接触并到达有源区域，第一和第二电极被埋在第一和第二沟槽中。由栅极绝缘膜，栅极电极，源极区域，基极区域和有源区域构成的MOS结构中形成有两个以上的沟道区域。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式