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41. 发明授权

US06812044B2 Advanced control for plasma process 有权
标题翻译：等离子体工艺的先进控制
公开(公告)号：US06812044B2
公开(公告)日：2004-11-02
申请号：US10324465
申请日：2002-12-19
申请人： Hsien-Kuang Chiu , Bor-Wen Chan , Baw-Ching Perng , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Hsien-Kuang Chiu , Bor-Wen Chan , Baw-Ching Perng , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： H01L2100
CPC分类号： H01J37/32935 , H01L21/67069 , H01L21/67253
摘要： A method for monitoring plasma parameters during a plasma process such as a plasma etching process, comparing the measured plasma parameters to predetermined parameter specifications, and either terminating the plasma process or modifying the plasma process in progress to re-establish the plasma parameters within the parameter specifications. The plasma parameters may be measured by the self-excited electron resonance spectroscopy (SEEKS) technique or by microwave interferometry.
摘要翻译：一种用于在诸如等离子体蚀刻工艺的等离子体工艺期间监测等离子体参数的方法，将测量的等离子体参数与预定参数规格进行比较，以及终止等离子体处理或修改正在进行的等离子体处理，以重新建立参数内的等离子体参数规格。等离子体参数可以通过自激电子共振光谱（SEEKS）技术或通过微波干涉测量来测量。

42. 发明申请

US20110312145A1 SOURCE AND DRAIN FEATURE PROFILE FOR IMPROVING DEVICE PERFORMANCE AND METHOD OF MANUFACTURING SAME 有权
标题翻译：用于改进装置性能的源和排出特征轮廓及其制造方法
公开(公告)号：US20110312145A1
公开(公告)日：2011-12-22
申请号：US12816519
申请日：2010-06-16
申请人： Ming-Huan Tsai , Chun-Fai Cheng , Hui Ouyang , Yuan-Hung Chiu , Yen-Ming Chen
发明人： Ming-Huan Tsai , Chun-Fai Cheng , Hui Ouyang , Yuan-Hung Chiu , Yen-Ming Chen
IPC分类号： H01L21/336
CPC分类号： H01L29/66515 , H01L21/265 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/7848
摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.
摘要翻译：公开了一种用于制造集成电路器件的集成电路器件和方法。所公开的方法提供对集成电路器件的表面接近度和尖端深度的改进的控制。在一个实施例中，该方法通过在器件的源极和漏极区域中形成掺杂区域和轻掺杂源极和漏极（LDD）区域来实现改进的控制。掺杂区域注入与LDD区域相反的掺杂剂类型。

43. 发明申请

US20080026518A1 Spacer layer etch method providing enhanced microelectronic device performance 有权
标题翻译：间隔层蚀刻方法提供增强的微电子器件性能
公开(公告)号：US20080026518A1
公开(公告)日：2008-01-31
申请号：US11495348
申请日：2006-07-28
申请人： Hung Der Su , Ju-Wang Hsu , Yi-Chun Huang , Shien-Yang Wu , Yung-Shun Chen , Tung-Heng Shie , Yuan-Hung Chiu , Jyh-Huei Chen , Jhon Jhy Liaw
发明人： Hung Der Su , Ju-Wang Hsu , Yi-Chun Huang , Shien-Yang Wu , Yung-Shun Chen , Tung-Heng Shie , Yuan-Hung Chiu , Jyh-Huei Chen , Jhon Jhy Liaw
IPC分类号： H01L21/8234
CPC分类号： H01L29/6656 , H01L29/665 , H01L29/6653
摘要： A method for forming a field effect transistor device employs a conformal spacer layer formed upon a gate electrode. The gate electrode is employed as a mask for forming a lightly doped extension region within the semiconductor substrate and the gate electrode and conformal spacer layer are employed as a mask for forming a source/drain region within the semiconductor substrate. An anisotropically etched shaped spacer material layer is formed upon the conformal spacer layer and isotropically etched to enhance exposure of the source/drain region prior to forming a silicide layer thereupon.
摘要翻译：用于形成场效应晶体管器件的方法使用形成在栅电极上的共形间隔层。栅电极用作在半导体衬底内形成轻掺杂延伸区的掩模，并且栅电极和共形间隔层用作在半导体衬底内形成源极/漏极区的掩模。在保形间隔层上形成各向异性蚀刻形状的间隔物层，并进行各向同性蚀刻，以在形成硅化物层之前增强源/漏区的曝光。

44. 发明授权

US07307009B2 Phosphoric acid free process for polysilicon gate definition 有权
标题翻译：多晶硅栅极定义的无磷酸工艺
公开(公告)号：US07307009B2
公开(公告)日：2007-12-11
申请号：US10999270
申请日：2004-11-29
申请人： Li-Te S. Lin , Fang-Cheng Chen , Huin-Jer Lin , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Li-Te S. Lin , Fang-Cheng Chen , Huin-Jer Lin , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： H01L21/00
CPC分类号： H01L21/31116 , H01L21/32137 , H01L21/32139
摘要： A method of defining a patterned, conductive gate structure for a MOSFET device on a semiconductor substrate includes forming a conductive layer over the semiconductor substrate and forming a capping insulator layer over the conductive layer. An anti-reflective coating (ARC) layer is formed over the capping insulator layer and a patterned photoresist shape is formed on the ARC layer. A first etch procedure using the photoresist shape as an etch mask defines a stack comprised of an ARC shape and a capping insulator shape. A second etch procedure using the stack as an etch mask defines the patterned, conductive gate structure in the conductive layer.
摘要翻译：在半导体衬底上限定用于MOSFET器件的图案化导电栅极结构的方法包括在半导体衬底上形成导电层并在导电层上形成覆盖绝缘体层。在覆盖绝缘体层上形成抗反射涂层（ARC）层，并且在ARC层上形成图案化的光刻胶形状。使用光致抗蚀剂形状作为蚀刻掩模的第一蚀刻步骤限定了由ARC形状和封盖绝缘体形状组成的堆叠。使用堆叠作为蚀刻掩模的第二蚀刻步骤限定了导电层中的图案化的导电栅极结构。

45. 发明授权

US07078351B2 Photoresist intensive patterning and processing 失效
标题翻译：光刻胶强化图案和加工
公开(公告)号：US07078351B2
公开(公告)日：2006-07-18
申请号：US10361875
申请日：2003-02-10
申请人： Yuan-Hung Chiu , Ming-Huan Tsai , Hun-Jan Tao , Jeng-Horng Chen
发明人： Yuan-Hung Chiu , Ming-Huan Tsai , Hun-Jan Tao , Jeng-Horng Chen
IPC分类号： H01L21/302
CPC分类号： H01L21/0276 , H01L21/0332 , H01L21/30604 , H01L21/3081 , H01L21/31116 , H01L21/31144 , H01L21/3144 , H01L21/3145 , H01L21/76802
摘要： A layer of Anti Reflective Coating (ARC) is first deposited over the surface of a silicon based or oxide based semiconductor surface, a dual hardmask is deposited over the surface of the layer of ARC. A layer of soft mask material is next coated over the surface of the dual hardmask layer, the layer of soft mask material is exposed, creating a soft mask material mask. The upper layer of the dual hardmask layer is next patterned in accordance with the soft mask material mask, the soft mask material mask is removed from the surface. The lower layer of the hardmask layer is then patterned after which the layer of ARC is patterned, both layers are patterned in accordance with the patterned upper layer of the dual hardmask layer. The substrate is now patterned in accordance with the patterned upper and lower layer of the dual hardmask layer and the patterned layer of ARC. The patterned upper and lower layers of the hardmask layer and the patterned layer of ARC are removed from the surface of the silicon based or oxide based semiconductor surface.
摘要翻译：首先将抗反射涂层（ARC）沉积在硅基或氧化物基半导体表面的表面上，双重硬掩模沉积在ARC层的表面上。然后将一层软掩模材料涂覆在双重硬掩模层的表面上，该软掩模材料层被暴露，形成柔软的掩模材料掩模。根据软掩模材料掩模，双硬掩模层的上层接下来图案化，从表面去除软掩模材料掩模。然后对硬掩模层的下层进行图案化，之后对ARC层进行构图，根据双重硬掩模层的图案化上层对两层进行图案化。衬底现在根据双重硬掩模层的图案化的上下层和ARC的图案化层进行图案化。从硅基或氧化物基半导体表面的表面去除硬掩模层的图案化的上层和下层以及ARC的图案化层。

46. 发明授权

US07074727B2 Process for improving dielectric properties in low-k organosilicate dielectric material 失效
标题翻译：改进低k有机硅酸盐介电材料介电性能的方法
公开(公告)号：US07074727B2
公开(公告)日：2006-07-11
申请号：US10615628
申请日：2003-07-09
申请人： Peng-Fu Hsu , Jyu-Horng Shieh , Yung-Cheng Lu , Hun-Jan Tao , Yuan-Hung Chiu
发明人： Peng-Fu Hsu , Jyu-Horng Shieh , Yung-Cheng Lu , Hun-Jan Tao , Yuan-Hung Chiu
IPC分类号： C08G77/00 , H01L21/768
CPC分类号： C08G77/38
摘要： Low-k organosilicate dielectric material can be exposed to a series of reagents, including a halogenation reagent, an alkylation reagent, and a termination reagent, in order to reverse degradation of dielectric properties caused by previous processing steps.
摘要翻译：低k有机硅酸盐电介质材料可以暴露于一系列试剂，包括卤化试剂，烷基化试剂和终止试剂，以反转由以前的处理步骤引起的介电性质的退化。

47. 发明申请

US20060148181A1 Strained channel CMOS device with fully silicided gate electrode 有权
标题翻译：具有完全硅化栅电极的应变通道CMOS器件
公开(公告)号：US20060148181A1
公开(公告)日：2006-07-06
申请号：US11026009
申请日：2004-12-31
申请人： Bor-Wen Chan , Yuan-Hung Chiu , Han-Jan Tao
发明人： Bor-Wen Chan , Yuan-Hung Chiu , Han-Jan Tao
IPC分类号： H01L21/8238
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L29/66545 , H01L29/66636 , H01L29/7843 , H01L29/7848 , Y10S438/938
摘要： A strained channel NMOS and PMOS device pair including fully silicided gate electrodes and method for forming the same, the method including providing a semiconductor substrate including NMOS and PMOS device regions including respective gate structures including polysilicon gate electrodes; forming recessed regions on either side of a channel region including at least one of the NMOS and PMOS device regions; backfilling portions of the recessed regions with a semiconducting silicon alloy to exert a strain on the channel region; forming offset spacers on either side of the gate structures; thinning the polysilicon gate electrodes to a silicidation thickness to allow full metal silicidation through the silicidation thickness; ion implanting the polysilicon gate electrodes to adjust a work function; and, forming a metal silicide through the silicidation thickness to form metal silicide gate electrodes.
摘要翻译：包括完全硅化栅电极的应变通道NMOS和PMOS器件对及其形成方法，该方法包括提供包含NMOS和PMOS器件区域的半导体衬底，PMOS器件区域包括包括多晶硅栅电极的各自的栅极结构; 在包括所述NMOS和PMOS器件区域中的至少一个的沟道区域的任一侧上形成凹陷区域; 用半导体硅合金回填凹陷区域，以在沟道区域上施加应变; 在栅极结构的任一侧上形成偏置间隔物; 将多晶硅栅电极减薄至硅化厚度，以允许通过硅化物厚度的全金属硅化物; 离子注入多晶硅栅电极以调节功函数; 并通过硅化物厚度形成金属硅化物以形成金属硅化物栅电极。

48. 发明授权

US06869868B2 Method of fabricating a MOSFET device with metal containing gate structures 有权
标题翻译：制造具有含金属栅极结构的MOSFET器件的方法
公开(公告)号：US06869868B2
公开(公告)日：2005-03-22
申请号：US10318459
申请日：2002-12-13
申请人： Hsien-Kuang Chiu , Fang-Cheng Chen , Haur-Ywh Chen , Hun-Jan Tao , Yuan-Hung Chiu
发明人： Hsien-Kuang Chiu , Fang-Cheng Chen , Haur-Ywh Chen , Hun-Jan Tao , Yuan-Hung Chiu
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/49 , H01L29/786 , H01L21/4763
CPC分类号： H01L29/785 , H01L21/28088 , H01L29/42384 , H01L29/4966 , H01L29/665 , H01L29/66795
摘要： A method of forming a composite gate structure for a planar MOSFET device, as well as for vertical, double gate, FINFET device, has been developed. The method features a composite gate structure comprised of an overlying silicon gate structure shape, and an underlying titanium nitride gate structure shape. The titanium nitride component allows a lower work function, and thus lower device operating voltages to be realized when compared to counterpart gate structures formed with only polysilicon. A novel, two step gate structure definition procedure, featuring an anisotropic first etch procedure for definition of the polysilicon gate structure shape, followed by a wet or dry isotopic second etch procedure for definition of the titanium nitride gate structure shape, is employed.
摘要翻译：已经开发了形成用于平面MOSFET器件的复合栅极结构以及用于垂直双栅极FINFET器件的方法。该方法具有由上覆硅栅极结构形状和下面的氮化钛栅极结构形状组成的复合栅极结构。与仅由多晶硅形成的对应栅极结构相比，氮化钛部件允许较低的功函数，因此降低器件工作电压。采用新颖的两步栅极结构定义方法，其特征在于用于定义多晶硅栅极结构形状的各向异性第一蚀刻工艺，随后是用于定义氮化钛栅极结构形状的湿式或干式同位素第二蚀刻工艺。

49. 发明授权

US06777340B1 Method of etching a silicon containing layer using multilayer masks 有权
标题翻译：使用多层掩模蚀刻含硅层的方法
公开(公告)号：US06777340B1
公开(公告)日：2004-08-17
申请号：US09949505
申请日：2001-09-10
申请人： Hsien-Kuang Chiu , Fang-Chang Chen , Hun-Jan Tao , Yuan-Hung Chiu , Jeng-Horng Chen
发明人： Hsien-Kuang Chiu , Fang-Chang Chen , Hun-Jan Tao , Yuan-Hung Chiu , Jeng-Horng Chen
IPC分类号： H01L21302
CPC分类号： H01L21/3081 , H01L21/32139
摘要： A new method is provided for the etch of ultra-small patterns in a silicon based surface. Under the first embodiment, a hardmask layer over a substrate and a layer of ARC over the hardmask layer are successively patterned. The patterned layer of ARC is removed, the remaining patterned hardmask layer is used as a mask for etching the substrate. Under the second embodiment, a first hardmask layer over a substrate, a second hardmask layer over the first hardmask layer and a layer of ARC over the second hardmask layer are successively patterned. The patterned layer of ARC and the second hardmask layer are removed, the remaining first patterned hardmask layer is used as a mask for etching the substrate.
摘要翻译：提供了一种用于在硅基表面中蚀刻超小图案的新方法。在第一实施例中，在衬底上的硬掩模层和硬掩模层上的ARC层被连续地图案化。去除图案化的ARC层，剩余的图案化硬掩模层用作蚀刻衬底的掩模。在第二实施例中，基板上的第一硬掩模层，第一硬掩模层上的第二硬掩模层和第二硬掩模层上的ARC层被连续地图案化。去除ARC和第二硬掩模层的图案层，剩余的第一图案化硬掩模层用作蚀刻衬底的掩模。

50. 发明授权

US06524938B1 Method for gate formation with improved spacer profile control 有权
标题翻译：具有改进的间隔物轮廓控制的栅极形成方法
公开(公告)号：US06524938B1
公开(公告)日：2003-02-25
申请号：US10075842
申请日：2002-02-13
申请人： Hun-Jan Tao , Yuan-Hung Chiu
发明人： Hun-Jan Tao , Yuan-Hung Chiu
IPC分类号： H01L213205
CPC分类号： H01L29/6656 , H01L21/28247 , H01L21/31116 , H01L29/4983
摘要： A new process is provided for the creation of an improved gate spacer profile. A layer of hardmask material is patterned over the surface of a layer of gate material. The layer of gate material is etch in accordance with the patterned layer of hardmask material, reducing the thickness of the patterned layer of hardmask material. A liner oxide is formed, a film of gate spacer material is deposited over the liner material. The layer of spacer material is etched, forming gate spacers and at the same time the remaining layer of hardmask material.
摘要翻译：提供了一种新的工艺来创建改进的浇口间隔件。在栅极材料层的表面上形成一层硬掩模材料。栅极材料层根据硬掩模材料的图案化层进行蚀刻，从而减小硬掩模材料图案化层的厚度。形成衬垫氧化物，栅衬垫材料的膜沉积在衬垫材料上。蚀刻隔离层材料层，形成栅极间隔物，同时形成剩余的硬掩模材料层。

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