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41. 发明申请

US20080201566A1 METHOD AND APPARATUS FOR MEASURING PIPELINE STALLS IN A MICROPROCESSOR 有权
标题翻译：用于测量微处理器中管道的方法和装置
公开(公告)号：US20080201566A1
公开(公告)日：2008-08-21
申请号：US11675112
申请日：2007-02-15
申请人： Venkat Rajeev Indukuru , Alexander Erik Mericas
发明人： Venkat Rajeev Indukuru , Alexander Erik Mericas
IPC分类号： G06F9/38
CPC分类号： G06F9/3867 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857 , G06F11/3423 , G06F11/3466 , G06F11/348 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A computer implemented method, apparatus, and computer program product for monitoring execution of instructions in an instruction pipeline. The process identifies a number of stall cycles for a group of instructions to complete execution. The process retrieves a deterministic latency pattern corresponding to the group of instructions. The process compares the number of stall cycles to the deterministic execution latency pattern. The process identifies the instruction as a dependent instruction in response to a determination that an instruction in the group of instructions completed a deterministic number of cycles after an antecedent instruction completed.
摘要翻译：一种计算机实现的方法，装置和计算机程序产品，用于监视指令流水线中的指令的执行。该过程识别一组完成执行的指令的停顿周期数。该过程检索对应于该组指令的确定性延迟模式。该过程将停顿周期数与确定性执行延迟模式进行比较。响应于确定指令组中的指令在前提指令完成之后完成确定性循环次数，该过程将该指令标识为依赖指令。

42. 发明授权

US07086035B1 Method and system for counting non-speculative events in a speculative processor 失效
标题翻译：用于计算投机处理器中非投机事件的方法和系统
公开(公告)号：US07086035B1
公开(公告)日：2006-08-01
申请号：US09310912
申请日：1999-05-13
申请人： Alexander Erik Mericas
发明人： Alexander Erik Mericas
IPC分类号： G06F9/45
CPC分类号： G06F9/3842 , G06F11/3409 , G06F11/3466 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A method and system for counting non-speculative events in a speculative processor is provided. The speculative processor contains a number of counters within a performance monitor for counting occurrences of specified events within a data processing system. An event to be monitored is specified. The specified event is monitored during the execution of instructions by the speculative processor. A count of occurrences of the specified event for all instructions executed by the speculative processor is generated, and a count of occurrences of the specified event for instructions completely executed by the speculative processor is generated. A difference between the count of occurrences of the specified event for all instructions and the count of occurrences of the specified event for all completed instructions may be generated as a count of occurrences of the specified event for instructions speculatively executed by the speculative processor.
摘要翻译：提供了一种用于计算推测处理器中的非投机事件的方法和系统。推测处理器在性能监视器中包含多个计数器，用于计数数据处理系统中指定事件的发生。指定要监视的事件。在由推测处理器执行指令期间监视指定的事件。产生由推测处理器执行的所有指令的指定事件的发生次数，并且生成由推测处理器完全执行的指令的指定事件的发生次数。所有指令的指定事件的发生次数和所有完成的指令的指定事件的发生次数之间的差异可以被生成为由推测性处理器推测执行的指令的指定事件的出现次数。

43. 发明授权

US06804770B2 Method and apparatus for using past history to avoid flush conditions in a microprocessor 失效
标题翻译：使用过去历史以避免微处理器中的冲洗状况的方法和装置
公开(公告)号：US06804770B2
公开(公告)日：2004-10-12
申请号：US09815553
申请日：2001-03-22
申请人： Douglas Robert Logan , Alexander Erik Mericas , William John Starke
发明人： Douglas Robert Logan , Alexander Erik Mericas , William John Starke
IPC分类号： G06F9312
CPC分类号： G06F9/3836 , G06F9/3861
摘要： A hazard prediction array consists of an array of saturating counters. The array is indexed through a portion of the instruction address. At issue, the hazard prediction array is referenced and a prediction is made as to whether the current instruction or group of instructions is likely to encounter a flush. If the prediction is that it will flush, the instruction is not issued until it is the next instruction to complete. If the prediction is that the instruction will not flush, it is issued as normal. At completion time, the prediction array is updated with the actual flush behavior. When an instruction is predicted to flush and, thus, not issued until it is the next to complete, the predictor may be updated as if the instruction did not flush.
摘要翻译：危险预测阵列由饱和计数器阵列组成。数组通过指令地址的一部分进行索引。在问题中，参考危险预测阵列，并且预测当前指令或指令组是否可能遇到冲水。如果预测会刷新，则直到完成下一条指令才会发出指令。如果预测是指令不会刷新，则正常发出。在完成时间，预测数组用实际的刷新行为更新。当预测指令刷新，因此在下一次完成之前不会发出指令，可能会更新预测器，就好像指令未刷新一样。

44. 发明授权

US06574727B1 Method and apparatus for instruction sampling for performance monitoring and debug 失效
标题翻译：用于性能监控和调试的指令采样方法和装置
公开(公告)号：US06574727B1
公开(公告)日：2003-06-03
申请号：US09435069
申请日：1999-11-04
申请人： Joel Roger Davidson , John Edward Derrick , Alexander Erik Mericas
发明人： Joel Roger Davidson , John Edward Derrick , Alexander Erik Mericas
IPC分类号： G06F900
CPC分类号： G06F9/3836 , G06F9/3017 , G06F9/3857 , G06F11/348 , G06F2201/88
摘要： A method and apparatus for selecting an instruction to be monitored within a pipelined processor in a data processing system is presented. A plurality of instructions are fetched, and the plurality of instructions are matched against at least one match condition to generate instructions that are eligible for sampling. The match conditions may include matching the opcode of an instruction, the pre-decode bits of an instruction, a type of instruction, or other conditions. The matched instructions may be marked using a match bit that accompanies the instruction through the selection process. The instructions eligible for sampling are then sampled to generate a sampled instruction. A sampled instruction may be marked with a sample bit that accompanies the instruction through the instruction execution process in order to monitor the sampled instruction while it is executing within the pipelined processor.
摘要翻译：提出了一种在数据处理系统中选择流水线处理器内要监视的指令的方法和装置。获取多个指令，并且将多个指令与至少一个匹配条件进行匹配，以生成符合抽样要求的指令。匹配条件可以包括匹配指令的操作码，指令的预解码位，指令的类型或其他条件。可以使用通过选择过程伴随指令的匹配位来标记匹配的指令。然后对符合抽样要求的指令进行采样以产生采样指令。采样指令可以通过指令执行过程伴随指令的采样位进行标记，以便在流水线处理器中执行时监视采样指令。

45. 发明授权

US06539500B1 System and method for tracing 失效
标题翻译：系统和追踪方法
公开(公告)号：US06539500B1
公开(公告)日：2003-03-25
申请号：US09428410
申请日：1999-10-28
申请人： James Allan Kahle , Alexander Erik Mericas , Kevin Franklin Reick , Joel M. Tendler
发明人： James Allan Kahle , Alexander Erik Mericas , Kevin Franklin Reick , Joel M. Tendler
IPC分类号： G06F1100
CPC分类号： G06F11/3636
摘要： The present invention discloses a system and method for implementing instruction tracing in a computer system and in particular a computer system with a tightly coupled shared processor central processor unit (CPU). Each of the processors are generally purpose processors that have been modified by design to allow an instruction to execute and simultaneously to be stored and forwarded to shared memory operable as a trace buffer. Since each processor is general purpose, the trace routine necessary for tracing, can by one of the routines or programs that can be written and executed on either of the processors. One of the processors can run, collect and analyze the executed and store instructions of the other processor. Since the processors can be on a single chip the shared memory bus that writes and reads the executed instructions can operate at high speed. Also since the trace function is part of the multiprocessor architecture its speed of operation will scale with the speed of the processors without modification.
摘要翻译：本发明公开了一种用于在计算机系统中实现指令跟踪的系统和方法，特别是具有紧耦合的共享处理器中央处理器单元（CPU）的计算机系统。每个处理器通常是通过设计修改的目的处理器，以允许指令执行并同时被存储并转发到可用作跟踪缓冲器的共享存储器。由于每个处理器是通用目的，因此可以通过其中一个可以在任一处理器上编写和执行的程序之一进行跟踪所需的跟踪例程。其中一个处理器可以运行，收集和分析其他处理器的执行和存储指令。由于处理器可以在单个芯片上，写入和读取执行的指令的共享存储器总线可以高速运行。此外，由于跟踪功能是多处理器架构的一部分，因此操作速度将随着处理器的速度而不变化。

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