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41. 发明申请

US20060205140A1 INTEGRATED CIRCUIT CAPACITOR HAVING ANTIREFLECTIVE DIELECTRIC 有权
标题翻译：具有抗反射电介质的集成电路电容器
公开(公告)号：US20060205140A1
公开(公告)日：2006-09-14
申请号：US11077074
申请日：2005-03-10
申请人： Bill Wofford , Blake Pasker , Xinfen Chen , Binghua Hu
发明人： Bill Wofford , Blake Pasker , Xinfen Chen , Binghua Hu
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L28/40 , Y10S438/952
摘要： A capacitor (100) is disclosed that is formed as part of an integrated circuit (IC) fabrication process. The capacitor (100) has conductive top and bottom electrodes (140, 144) and a nonconductive capacitor dielectric (142). In one example, the dielectric (142) includes first and second thin dielectric layers (112, 114) that sandwich a layer of antireflective material (118). The thin layers (112, 114) provide the dielectric behavior necessary for the capacitor while the antireflective layer (118) promotes reduced feature sizes by mitigating reflected standing waves, among other things.
摘要翻译：公开了作为集成电路（IC）制造工艺的一部分形成的电容器（100）。电容器（100）具有导电的顶部和底部电极（140,144）和非导电电容器电介质（142）。在一个示例中，电介质（142）包括夹着抗反射材料层（118）的第一和第二薄介电层（112,114）。薄层（112,114）提供电容器所需的电介质行为，而抗反射层（118）除其他之外通过减轻反射的驻波来促进减小的特征尺寸。

42. 发明申请

US20120177684A1 PAPILLOMAVIRUS VACCINE COMPOSITIONS 审中-公开
标题翻译：肉毒杆菌组合物
公开(公告)号：US20120177684A1
公开(公告)日：2012-07-12
申请号：US13423847
申请日：2012-03-19
申请人： Janine T. Bryan , Michelle K. Brownlow , Li Shi , Danilo Casimiro , William L. McClements , Brian K. Meyer , Binghua Hu
发明人： Janine T. Bryan , Michelle K. Brownlow , Li Shi , Danilo Casimiro , William L. McClements , Brian K. Meyer , Binghua Hu
IPC分类号： A61K39/12 , A61P31/20 , A61P37/04
CPC分类号： A61K39/12 , A61K2039/5258 , A61K2039/55505 , A61K2039/55577 , A61K2039/70 , C12N7/00 , C12N2710/20023 , C12N2710/20034
摘要： The present invention relates to pharmaceutical compositions comprising virus-like particles (VLPs) of HPV, said VLPs adsorbed to an aluminum adjuvant, and an ISCOM-type adjuvant comprising a saponin, cholesterol, and a phospholipid. In preferred embodiments, the aluminum adjuvant comprises amorphous aluminum hydroxyphosphate sulfate. Another aspect of the invention provides multi-dose HPV vaccine formulations comprising HPV VLPs and an antimicrobial preservative selected from the group consisting of: m-cresol, phenol and benzyl alcohol. Also provided are methods of using the disclosed pharmaceutical compositions and formulations to induce an immune response against HPV in a human patient and to prevent HPV infection.
摘要翻译：本发明涉及包含HPV病毒样颗粒（VLP），所述VLP吸附于铝佐剂的ISMA型佐剂和包含皂角苷，胆固醇和磷脂的ISCOM型佐剂的药物组合物。在优选的实施方案中，铝佐剂包括无定形的羟基磷酸氢铝硫酸盐。本发明的另一方面提供了包含HPV VLP和选自间甲酚，苯酚和苄醇的抗微生物防腐剂的多剂量HPV疫苗制剂。还提供了使用所公开的药物组合物和制剂在人类患者中诱导针对HPV的免疫应答并防止HPV感染的方法。

43. 发明授权

US08154101B2 High voltage diode with reduced substrate injection 有权
公开(公告)号：US08154101B2
公开(公告)日：2012-04-10
申请号：US12537318
申请日：2009-08-07
申请人： Sameer P. Pendharkar , Binghua Hu
发明人： Sameer P. Pendharkar , Binghua Hu
IPC分类号： H01L29/861
CPC分类号： H01L29/861 , H01L21/761 , H01L21/76264 , H01L27/0629 , H01L29/417 , H01L29/66136
摘要： A high voltage diode in which the n-type cathode is surrounded by an uncontacted heavily doped n-type ring to reflect injected holes back into the cathode region for recombination or collection is disclosed. The dopant density in the heavily doped n-type ring is preferably 100 to 10,000 times the dopant density in the cathode. The heavily doped n-type region will typically connect to an n-type buried layer under the cathode. The heavily doped n-type ring is optimally positioned at least one hole diffusion length from cathode contacts. The disclosed high voltage diode may be integrated into an integrated circuit without adding process steps.

44. 发明授权

US08110414B2 Forming integrated circuit devices with metal-insulator-metal capacitors using selective etch of top electrodes 有权
标题翻译：使用金属绝缘体金属电容器形成集成电路器件，使用顶部电极的选择性蚀刻
公开(公告)号：US08110414B2
公开(公告)日：2012-02-07
申请号：US12433042
申请日：2009-04-30
申请人： Marshall O. Cathey, Jr. , Pushpa Mahalingam , Weidong Tian , David C. Guiling , Xinfen Chen , Binghua Hu , Sopa Chevacharoenkul
发明人： Marshall O. Cathey, Jr. , Pushpa Mahalingam , Weidong Tian , David C. Guiling , Xinfen Chen , Binghua Hu , Sopa Chevacharoenkul
IPC分类号： H01L31/26 , H01L21/66
CPC分类号： H01L27/0805 , H01L22/26 , H01L28/40
摘要： A method of forming integrated circuits (IC) having at least one metal insulator metal (MIM) capacitor. A bottom electrode is formed on a predetermined region of a semiconductor surface of a substrate. At least one dielectric layer including silicon is formed on the bottom electrode, wherein a thickness of the dielectric layer is
摘要翻译：一种形成具有至少一个金属绝缘体金属（MIM）电容器的集成电路（IC）的方法。底部电极形成在基板的半导体表面的预定区域上。在底部电极上形成至少一层包括硅的电介质层，其中电介质层的厚度<1000。在电介质层上形成顶部电极层。在顶部电极层上形成图案化掩模层。至少部分地使用干法刻蚀的蚀刻用于蚀刻图案化掩模层外部的顶部电极层，以到达介电层，该电介质层去除了介电层厚度的100埃。干蚀刻工艺包括使用包含气体的第一卤素，包含氟的第二卤素和包含氟的气体和载气。

45. 发明授权

US07902033B2 Methods and devices for a high-k stacked capacitor 有权
标题翻译：高k堆叠电容器的方法和装置
公开(公告)号：US07902033B2
公开(公告)日：2011-03-08
申请号：US12029798
申请日：2008-02-12
申请人： Byron Lovell Williams , Maxwell Walthour Lippitt, III , Betty Mercer , Scott Montgomery , Binghua Hu
发明人： Byron Lovell Williams , Maxwell Walthour Lippitt, III , Betty Mercer , Scott Montgomery , Binghua Hu
IPC分类号： H01L21/20
CPC分类号： H01L28/91
摘要： An embodiment generally relates a method of forming capacitors. The method includes forming a plurality of holes within a protective overcoat or backend dielectric layer of an integrated circuit and depositing multiple layers of metal, each layer of metal electrically tied to an associated electrode. The method also includes alternately depositing multiple layers of dielectric between the multiple layers of metal and coupling a bottom layer of the multiple layers of metal to a contact node in a top metal layer of the integrated circuit.
摘要翻译：实施例通常涉及形成电容器的方法。该方法包括在集成电路的保护外涂层或后端电介质层内形成多个孔，并沉积多层金属，每层金属电连接到相关电极。该方法还包括交替地在多层金属之间沉积多层电介质，并将多层金属的底层耦合到集成电路的顶层金属层中的接触节点。

46. 发明申请

US20070105332A1 INTEGRATED CIRCUIT CAPACITOR HAVING ANTIREFLECTIVE DIELECTRIC 有权
标题翻译：具有抗反射电介质的集成电路电容器
公开(公告)号：US20070105332A1
公开(公告)日：2007-05-10
申请号：US11470023
申请日：2006-09-05
申请人： Bill Wofford , Blake Pasker , Xinfen Chen , Binghua Hu
发明人： Bill Wofford , Blake Pasker , Xinfen Chen , Binghua Hu
IPC分类号： H01L29/94 , H01L21/20
CPC分类号： H01L28/40 , Y10S438/952
摘要： A capacitor (100) is disclosed that is formed as part of an integrated circuit (IC) fabrication process. The capacitor (100) has conductive top and bottom electrodes (140, 144) and a nonconductive capacitor dielectric (142). In one example, the dielectric (142) includes first and second thin dielectric layers (112, 114) that sandwich a layer of antireflective material (118). The thin layers (112, 114) provide the dielectric behavior necessary for the capacitor while the antireflective layer (118) promotes reduced feature sizes by mitigating reflected standing waves, among other things.
摘要翻译：公开了作为集成电路（IC）制造工艺的一部分形成的电容器（100）。电容器（100）具有导电的顶部和底部电极（140,144）和非导电电容器电介质（142）。在一个示例中，电介质（142）包括夹着抗反射材料层（118）的第一和第二薄介电层（112,114）。薄层（112,114）提供电容器所需的电介质行为，而抗反射层（118）除其他之外通过减轻反射的驻波来促进减小的特征尺寸。

47. 发明授权

US07118959B2 Integrated circuit capacitor having antireflective dielectric 有权
标题翻译：具有抗反射电介质的集成电路电容器
公开(公告)号：US07118959B2
公开(公告)日：2006-10-10
申请号：US11077074
申请日：2005-03-10
申请人： Bill Alan Wofford , Blake Ryan Pasker , Xinfen Chen , Binghua Hu
发明人： Bill Alan Wofford , Blake Ryan Pasker , Xinfen Chen , Binghua Hu
IPC分类号： H01L21/8242
CPC分类号： H01L28/40 , Y10S438/952
摘要： A capacitor (100) is disclosed that is formed as part of an integrated circuit (IC) fabrication process. The capacitor (100) has conductive top and bottom electrodes (140, 144) and a nonconductive capacitor dielectric (142). In one example, the dielectric (142) includes first and second thin dielectric layers (112, 114) that sandwich a layer of antireflective material (118). The thin layers (112, 114) provide the dielectric behavior necessary for the capacitor while the antireflective layer (118) promotes reduced feature sizes by mitigating reflected standing waves, among other things.
摘要翻译：公开了作为集成电路（IC）制造工艺的一部分形成的电容器（100）。电容器（100）具有导电的顶部和底部电极（140,144）和非导电电容器电介质（142）。在一个示例中，电介质（142）包括夹着抗反射材料层（118）的第一和第二薄介电层（112,114）。薄层（112,114）提供电容器所需的电介质行为，而抗反射层（118）除其他之外通过减轻反射的驻波来促进减小的特征尺寸。

48. 发明授权

US08334190B2 Single step CMP for polishing three or more layer film stacks 有权
标题翻译：用于抛光三层或更多层薄膜叠层的单步CMP
公开(公告)号：US08334190B2
公开(公告)日：2012-12-18
申请号：US12776057
申请日：2010-05-07
申请人： Eugene C. Davis , Binghua Hu , Sopa Chevacharoenkul , Prakash D. Dev
发明人： Eugene C. Davis , Binghua Hu , Sopa Chevacharoenkul , Prakash D. Dev
IPC分类号： H01L21/763 , H01L21/302
CPC分类号： C09G1/02 , H01L21/31053 , H01L21/3212 , H01L22/12 , H01L22/26
摘要： A one-step CMP process for polishing three or more layer film stacks on a wafer having a multilayer film stack thereon including a silicon nitride (SiNx) layer on its semiconductor surface, and a silicon oxide layer on the SiNx layer, wherein trench access vias extend through the silicon oxide layer and SiNx layer to trenches formed into the semiconductor surface, and wherein a polysilicon layer fills the trench access vias, fills the trenches, and is on the silicon oxide layer. CMP polishes the multilayer film stack with a slurry including slurry particles including at least one of silica and ceria. The CMP provides a removal rate (RR) for the polysilicon layer > a RR for the silicon oxide layer > a RR for the SiNx layer. The CMP process is continued to remove the polysilicon layer, silicon oxide layer and a portion of the SiNx layer to stop on the SiNx layer. Optical endpointing during CMP can provide a predetermined remaining thickness range for the SiNx layer.
摘要翻译：一种用于在其上具有多层膜堆叠的晶片上的三层或更多层膜堆叠的半导体表面上的氮化硅（SiNx）层和SiN x层上的氧化硅层的一步CMP工艺，其中沟槽通孔延伸穿过硅氧化物层和SiNx层到形成半导体表面的沟槽，并且其中多晶硅层填充沟槽接通通孔，填充沟槽并且在氧化硅层上。 CMP用包括二氧化硅和二氧化铈中的至少一种的浆料颗粒的浆料抛光多层膜堆叠。 CMP提供多晶硅层的去除率（RR）>硅氧化物层的RR> SiNx层的RR。继续进行CMP处理以去除SiN x层上的多晶硅层，氧化硅层和SiNx层的一部分。 CMP期间的光学终点可以为SiNx层提供预定的剩余厚度范围。

49. 发明授权

US08309423B2 High voltage diode with reduced substrate injection 有权
标题翻译：具有降低衬底注入的高压二极管
公开(公告)号：US08309423B2
公开(公告)日：2012-11-13
申请号：US13409689
申请日：2012-03-01
申请人： Sameer P. Pendharkar , Binghua Hu
发明人： Sameer P. Pendharkar , Binghua Hu
IPC分类号： H01L29/861
CPC分类号： H01L29/861 , H01L21/761 , H01L21/76264 , H01L27/0629 , H01L29/417 , H01L29/66136
摘要： A high voltage diode in which the n-type cathode is surrounded by an uncontacted heavily doped n-type ring to reflect injected holes back into the cathode region for recombination or collection is disclosed. The dopant density in the heavily doped n-type ring is preferably 100 to 10,000 times the dopant density in the cathode. The heavily doped n-type region will typically connect to an n-type buried layer under the cathode. The heavily doped n-type ring is optimally positioned at least one hole diffusion length from cathode contacts. The disclosed high voltage diode may be integrated into an integrated circuit without adding process steps.
摘要翻译：公开了一种高压二极管，其中n型阴极由未接触的重掺杂n型环包围以将注入的孔反射回阴极区域进行复合或收集。重掺杂n型环中的掺杂剂密度优选为阴极中掺杂剂密度的100至10,000倍。重掺杂的n型区通常连接到阴极下方的n型掩埋层。重掺杂的n型环优选地从阴极触点定位至少一个孔扩散长度。所公开的高电压二极管可以集成到集成电路中，而不需要添加工艺步骤。

50. 发明授权

US07989232B2 Method of using electrical test structure for semiconductor trench depth monitor 有权
标题翻译：半导体沟槽深度监测仪使用电气测试结构的方法
公开(公告)号：US07989232B2
公开(公告)日：2011-08-02
申请号：US11531103
申请日：2006-09-12
申请人： Qingfeng Wang , Sameer P. Pendharkar , Binghua Hu
发明人： Qingfeng Wang , Sameer P. Pendharkar , Binghua Hu
IPC分类号： H01L21/66 , H01L27/07
CPC分类号： H01L22/12 , H01L29/0649 , H01L29/8605
摘要： Embodiments provide a method and device for electrically monitoring trench depths in semiconductor devices. To electrically measure a trench depth, a pinch resistor can be formed in a deep well region on a semiconductor substrate. A trench can then be formed in the pinch resistor. The trench depth can be determined by an electrical test of the pinch resistor. The disclosed method and device can provide statistical data analysis across a wafer and can be implemented in production scribe lanes as a process monitor. The disclosed method can also be useful for determining device performance of LDMOS transistors. The on-state resistance (Rdson) of the LDMOS transistors can be correlated to the electrical measurement of the trench depth.
摘要翻译：实施例提供了用于电监测半导体器件中的沟槽深度的方法和装置。为了电测量沟槽深度，可以在半导体衬底上的深阱区域中形成夹持电阻器。然后可以在夹持电阻器中形成沟槽。沟槽深度可以通过夹持电阻器的电气测试来确定。所公开的方法和装置可以跨晶片提供统计数据分析，并且可以在作为过程监视器的生产划线中实现。所公开的方法也可用于确定LDMOS晶体管的器件性能。 LDMOS晶体管的导通电阻（Rdson）可以与沟槽深度的电测量相关。

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