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41. 发明授权

US06936508B2 Metal gate MOS transistors and methods for making the same 有权
公开(公告)号：US06936508B2
公开(公告)日：2005-08-30
申请号：US10661130
申请日：2003-09-12
申请人： Mark Visokay , Luigi Colombo , James J. Chambers
发明人： Mark Visokay , Luigi Colombo , James J. Chambers
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/49 , H01L29/51 , H01L21/3205 , H01L29/76
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/823842 , H01L29/513 , H01L29/517 , H01L29/665
摘要： Semiconductor devices and fabrication methods are provided, in which metal transistor gates are provided for MOS transistors. Metal boride is formed above a gate dielectric to create PMOS gate structures and metal nitride is formed over a gate dielectric to provide NMOS gate structures. The metal portions of the gate structures are formed from an initial starting material that is either a metal boride or a metal nitride, after which the starting material is provided with boron or nitrogen in one of the PMOS and NMOS regions through implantation, diffusion, or other techniques, either before or after formation of the conductive upper material, and before or after gate patterning. The change in the boron or nitrogen content of the starting material provides adjustment of the material work function, thereby tuning the threshold voltage of the resulting PMOS or NMOS transistors.

42. 发明授权

US06444542B2 Integrated circuit and method 有权
标题翻译：集成电路及方法
公开(公告)号：US06444542B2
公开(公告)日：2002-09-03
申请号：US09826283
申请日：2001-04-03
申请人： Theodore S. Moise , Guoqiang Xing , Mark Visokay , Justin F. Gaynor , Stephen R. Gilbert , Francis Celii , Scott R. Summerfelt , Luigi Colombo
发明人： Theodore S. Moise , Guoqiang Xing , Mark Visokay , Justin F. Gaynor , Stephen R. Gilbert , Francis Celii , Scott R. Summerfelt , Luigi Colombo
IPC分类号： H01L2176
CPC分类号： H01L27/11502 , H01L21/0332 , H01L21/31116 , H01L21/31144 , H01L27/10852 , H01L27/11507 , H01L28/55
摘要： A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.
摘要翻译：在电极之间与电介质之间的电介质与绝缘扩散阻挡层之间的电介质接触电容器的通孔蚀刻包括基于F的电介质蚀刻和基于Cl和F的势垒蚀刻的两步蚀刻。

43. 发明申请

US20060292790A1 DUAL WORK FUNCTION GATE ELECTRODES USING DOPED POLYSILICON AND A METAL SILICON GERMANIUM COMPOUND 有权
标题翻译：使用掺杂多晶硅和金属硅锗化合物的双功能门电极
公开(公告)号：US20060292790A1
公开(公告)日：2006-12-28
申请号：US11463128
申请日：2006-08-08
申请人： Antonio Rotondaro , Mark Visokay , Luigi Colombo
发明人： Antonio Rotondaro , Mark Visokay , Luigi Colombo
IPC分类号： H01L21/8242 , H01L29/76
CPC分类号： H01L21/28097 , H01L21/823842 , H01L29/4975
摘要： A dielectric layer (50) is formed over a semiconductor (10) that contains a first region (20) and a second region (30). A polysilicon layer is formed over the dielectric layer (50) and over the first region (20) and the second region (30). The polysilicon layer can comprise 0 to 50 atomic percent of germanium. A metal layer is formed over the polysilicon layer and one of the regions and reacted with the underlying polysilicon layer to form a metal silicide or a metal germano silicide. The polysilicon and metal silicide or germano silicide regions are etched to form transistor gate regions (60) and (90) respectively. If desired a cladding layer (100) can be formed above the metal gate structures.
摘要翻译：在包含第一区域（20）和第二区域（30）的半导体（10）上形成介电层（50）。在电介质层（50）上并在第一区域（20）和第二区域（30）之上形成多晶硅层。多晶硅层可以包含0至50原子％的锗。在多晶硅层和其中一个区域上形成金属层，并与下面的多晶硅层反应形成金属硅化物或金属锗化硅。蚀刻多晶硅和金属硅化物或锗硅化物区域以分别形成晶体管栅极区域（60）和（90）。如果需要，可以在金属栅极结构上方形成包覆层（100）。

44. 发明申请

US20060244045A1 MOS Transistor Gates with Doped Silicide and Methods for Making the Same 审中-公开
标题翻译：具有掺杂硅化物的MOS晶体管门和制造相同的方法
公开(公告)号：US20060244045A1
公开(公告)日：2006-11-02
申请号：US11457203
申请日：2006-07-13
申请人： Mark Visokay , Luigi Colombo
发明人： Mark Visokay , Luigi Colombo
IPC分类号： H01L29/788
CPC分类号： H01L21/823842 , H01L21/823835
摘要： Semiconductor devices and fabrication methods are presented, in which transistor gate structures are created using doped metal silicide materials. Upper and lower metal silicides are formed above a gate dielectric, wherein the lower metal silicide is doped with n-type impurities for NMOS gates and with p-type impurities for PMOS gates, and wherein a silicon may, but need not be formed between the upper and lower metal silicides. The lower metal silicide can be deposited directly, or may be formed through reaction of deposited metal and poly-silicon, and the lower silicide can be doped by diffusion or implantation, before or after gate patterning.
摘要翻译：提出了半导体器件和制造方法，其中使用掺杂的金属硅化物材料制造晶体管栅极结构。上和下金属硅化物形成在栅极电介质上方，其中下部金属硅化物掺杂用于NMOS栅极的n型杂质和用于PMOS栅极的p型杂质，并且其中硅可以但不必形成在上下金属硅化物。可以直接沉积下金属硅化物，或者可以通过沉积的金属和多晶硅的反应形成下部金属硅化物，并且可以在栅极图案化之前或之后通过扩散或注入掺杂下硅化物。

45. 发明申请

US20060138556A1 Gate dielectric and method 有权
公开(公告)号：US20060138556A1
公开(公告)日：2006-06-29
申请号：US11339393
申请日：2006-01-25
申请人： Mark Visokay , Antonio Rotondaro , Luigi Colombo
发明人： Mark Visokay , Antonio Rotondaro , Luigi Colombo
IPC分类号： H01L29/94
CPC分类号： H01L21/823857 , H01L21/823842
摘要： A MOSFET structure with high-k gate dielectric layer and silicon or metal gates, amorphizing treatment of the high-k gate dielectric layer as with a plasma or ion implantation.

46. 发明申请

US20050136605A1 MOS transistor gates with thin lower metal silicide and methods for making the same 有权
标题翻译：具有薄的下金属硅化物的MOS晶体管栅极及其制造方法
公开(公告)号：US20050136605A1
公开(公告)日：2005-06-23
申请号：US10745454
申请日：2003-12-22
申请人： Robert Murto , Luigi Colombo , Mark Visokay
发明人： Robert Murto , Luigi Colombo , Mark Visokay
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/49 , H01L21/3205 , H01L21/44
CPC分类号： H01L29/4975 , H01L21/28097 , H01L21/823835 , H01L29/665 , H01L29/6659
摘要： Methods are presented for fabricating transistor gate structures, wherein upper and lower metal suicides are formed above a gate dielectric. In one example, the lower silicide is formed by depositing a thin first silicon-containing material over the gate dielectric, which is implanted and then reacted with a first metal by annealing to form the lower silicide. A capping layer can be formed over the first metal prior to annealing, to prevent oxidation of the metal prior to silicidation, and a barrier layer can be formed over the lower silicide to prevent reaction with subsequently formed silicon material. In another example, the lower silicide is a multilayer silicide structure including a plurality of metal silicide sublayers.
摘要翻译：呈现用于制造晶体管栅极结构的方法，其中上和下金属硅化物形成在栅极电介质上方。在一个示例中，下硅化物通过在栅极电介质上沉积薄的第一含硅材料而形成，其被注入，然后通过退火与第一金属反应以形成下硅化物。在退火之前可以在第一金属上形成覆盖层，以防止在硅化物之前金属的氧化，并且可以在下硅化物上形成阻挡层以防止随后形成的硅材料的反应。在另一个实例中，下硅化物是包括多个金属硅化物层的多层硅化物结构。

47. 发明授权

US06902939B2 Integrated circuit and method 有权
标题翻译：集成电路及方法
公开(公告)号：US06902939B2
公开(公告)日：2005-06-07
申请号：US10223643
申请日：2002-08-19
申请人： Theodore S. Moise , Guoqiang Xing , Mark Visokay , Justin F. Gaynor , Stephen R. Gilbert , Francis Celii , Scott R. Summerfelt , Luigi Colombo
发明人： Theodore S. Moise , Guoqiang Xing , Mark Visokay , Justin F. Gaynor , Stephen R. Gilbert , Francis Celii , Scott R. Summerfelt , Luigi Colombo
IPC分类号： H01L21/302 , H01L21/02 , H01L21/033 , H01L21/3065 , H01L21/311 , H01L21/8242 , H01L21/8246 , H01L27/115 , H01L21/00
CPC分类号： H01L27/11502 , H01L21/0332 , H01L21/31116 , H01L21/31144 , H01L27/10852 , H01L27/11507 , H01L28/55
摘要： A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.
摘要翻译：在电极之间与电介质之间的电介质与绝缘扩散阻挡层之间的电介质接触电容器的通孔蚀刻包括基于F的电介质蚀刻和基于Cl和F的势垒蚀刻的两步蚀刻。

48. 发明申请

US20050070062A1 MOS transistor gates with doped silicide and methods for making the same 有权
标题翻译：具有掺杂硅化物的MOS晶体管栅极及其制造方法
公开(公告)号：US20050070062A1
公开(公告)日：2005-03-31
申请号：US10674771
申请日：2003-09-30
申请人： Mark Visokay , Luigi Colombo
发明人： Mark Visokay , Luigi Colombo
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/823835
摘要： Semiconductor devices and fabrication methods are presented, in which transistor gate structures are created using doped metal silicide materials. Upper and lower metal silicides are formed above a gate dielectric, wherein the lower metal silicide is doped with n-type impurities for NMOS gates and with p-type impurities for PMOS gates, and wherein a silicon may, but need not be formed between the upper and lower metal silicides. The lower metal silicide can be deposited directly, or may be formed through reaction of deposited metal and poly-silicon, and the lower silicide can be doped by diffusion or implantation, before or after gate patterning.
摘要翻译：提出了半导体器件和制造方法，其中使用掺杂的金属硅化物材料制造晶体管栅极结构。上和下金属硅化物形成在栅极电介质上方，其中下部金属硅化物掺杂用于NMOS栅极的n型杂质和用于PMOS栅极的p型杂质，并且其中硅可以但不必形成在上下金属硅化物。可以直接沉积下金属硅化物，或者可以通过沉积的金属和多晶硅的反应形成下部金属硅化物，并且可以在栅极图案化之前或之后通过扩散或注入来掺杂下硅化物。

49. 发明授权

US06828200B2 Multistage deposition that incorporates nitrogen via an intermediate step 有权
标题翻译：通过中间步骤结合氮的多级沉积
公开(公告)号：US06828200B2
公开(公告)日：2004-12-07
申请号：US10336441
申请日：2003-01-03
申请人： James Joseph Chambers , Mark Visokay , Luigi Colombo
发明人： James Joseph Chambers , Mark Visokay , Luigi Colombo
IPC分类号： H01L21336
CPC分类号： H01L21/022 , H01L21/02148 , H01L21/02266 , H01L21/02271 , H01L21/02329 , H01L21/02337 , H01L21/0234 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/3144 , H01L21/31645 , H01L29/513 , H01L29/517 , H01L29/518
摘要： The present invention forms a nitrided dielectric layer without substantial harm to a semiconductor layer on which the dielectric layer is formed. The invention employs a multi-stage process in which dielectric sub-layers are individually nitrided before formation of a next dielectric sub-layer. The net result is a nitrided multi-layered dielectric layer comprised of a plurality of dielectric sub-layers wherein the sub-layers have been individually deposited and incorporated with nitrogen.
摘要翻译：本发明形成氮化电介质层，而对形成介电层的半导体层没有实质的损害。本发明采用多级工艺，其中在形成下一个电介质子层之前，将电介质子层单独氮化。最终结果是由多个电介质子层组成的氮化多层电介质层，其中子层已经被单独沉积并与氮结合。

50. 发明授权

US06750126B1 Methods for sputter deposition of high-k dielectric films 有权
标题翻译：溅射沉积高k电介质膜的方法
公开(公告)号：US06750126B1
公开(公告)日：2004-06-15
申请号：US10338276
申请日：2003-01-08
申请人： Mark Visokay , James Joseph Chambers , Luigi Colombo , Antonio Luis Pacheco Rotondaro
发明人： Mark Visokay , James Joseph Chambers , Luigi Colombo , Antonio Luis Pacheco Rotondaro
IPC分类号： H01L213205
CPC分类号： H01L21/28202 , H01L21/28035 , H01L21/28194 , H01L21/314 , H01L21/3143 , H01L21/31645 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/6659
摘要： Methods are disclosed for fabricating transistor gate structures and high-k dielectric layers therefor by sputter deposition, in which nitridation and/or oxidation or other adverse reaction of the semiconductor material is reduced or minimized by reducing the bombardment of the semiconductor body by positively charged reactive ions such as oxygen ions or nitrogen ions during the sputter deposition process. The sputtering operation may be a two-step process in which ionic bombardment of the semiconductor material is minimized in an initial deposition step to form a first layer portion covering the semiconductor body, and the second step completes the desired high-k dielectric layer. Mitigation of unwanted nitridation and/or oxidation or other adverse reaction is achieved through one, some, or all of high sputtering deposition pressure, repulsive wafer biasing, increased wafer-plasma spacing, low partial pressures for reactant gases, and low sputtering powers or power densities.
摘要翻译：公开了用于通过溅射沉积来制造晶体管栅极结构和高k电介质层的方法，其中半导体材料的氮化和/或氧化或其它不利反应被减小或最小化，通过减少半导体主体的带正电荷的反应离子如氧离子或氮离子在溅射沉积过程中。溅射操作可以是在初始沉积步骤中使半导体材料的离子轰击最小化以形成覆盖半导体本体的第一层部分的两步法，并且第二步骤完成所需的高k电介质层。通过高溅射沉积压力，排斥晶片偏置，增加的晶片 - 等离子体间隔，反应气体的低分压以及低溅射功率或功率的一种，一些或全部来实现减少不希望的氮化和/或氧化或其它不利反应密度

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