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41. 发明授权

US07581139B2 Distinguishing between two classes of trace information 有权
标题翻译：区分两类跟踪信息
公开(公告)号：US07581139B2
公开(公告)日：2009-08-25
申请号：US11467746
申请日：2006-08-28
申请人： Manisha Agarwala
发明人： Manisha Agarwala
IPC分类号： G06F11/00
CPC分类号： G06F11/348
摘要： A method of tracing activity of a data processor generates a trace data stream during a normal background mode and a foreground mode while servicing a real time interrupt during an emulation halt. An Interrupt During Suspend bit is set in foreground modes and transmitted in the trace data stream to distinguish the trace data streams between background mode and foreground mode.
摘要翻译：跟踪数据处理器的活动的方法在正常后台模式和前台模式期间生成跟踪数据流，同时在仿真停止期间服务于实时中断。中断在暂停期间，位在前台模式下设置，并在跟踪数据流中传输，以区分背景模式和前台模式之间的跟踪数据流。

42. 发明授权

US07444504B2 Tracing through reset 有权
标题翻译：跟踪通过重置
公开(公告)号：US07444504B2
公开(公告)日：2008-10-28
申请号：US11820546
申请日：2007-06-20
申请人： Manisha Agarwala , Lewis Nardini
发明人： Manisha Agarwala , Lewis Nardini
IPC分类号： G06F11/00
CPC分类号： G06F11/3636 , G06F11/3656
摘要： A method of tracing a data processor upon reset of the data processor. A data processor reset signal resets the data processor, part of trace collection hardware and does not reset remaining parts of trace collection hardware. The data processor reset signal may be not owned, owned by an application program or owned by a debugger. The partial not reset of the trace collection hardware occurs only upon a data processor reset signal owned by the debugger. A trace logic reset signal resets both the data processor and the trace collection hardware when not owned. This trace logic reset signal resets the data processor only when owned by the debugger and resets the trace collection hardware when owned by an application program.
摘要翻译：一种在数据处理器复位时跟踪数据处理器的方法。数据处理器复位信号复位数据处理器，跟踪收集硬件的一部分，不会复位跟踪收集硬件的剩余部分。数据处理器复位信号可以不是由应用程序所拥有或由调试器拥有的。跟踪收集硬件的部分不复位仅在调试器所拥有的数据处理器复位信号时发生。跟踪逻辑复位信号在不拥有时复位数据处理器和跟踪收集硬件。该跟踪逻辑复位信号仅在调试器拥有时复位数据处理器，并在应用程序拥有时重置跟踪收集硬件。

43. 发明申请

US20080126871A1 Token-Based Trace System 有权
标题翻译：基于令牌的跟踪系统
公开(公告)号：US20080126871A1
公开(公告)日：2008-05-29
申请号：US11468114
申请日：2006-08-29
申请人： Lewis Nardini , Manisha Agarwala , Neil Common
发明人： Lewis Nardini , Manisha Agarwala , Neil Common
IPC分类号： G06F11/36
CPC分类号： G06F11/3636 , G06F11/3648
摘要： A system comprising a target hardware comprising multiple processor cores and an application. The system also comprises a host computer coupled to the target hardware by way of a connection and adapted to debug the application by receiving trace information via the connection. In determining which trace information to send via the connection, the target hardware gives priority to trace information generated by a primary processor core associated with a token over trace information generated by a secondary processor core not associated with the token. The token is associated with one of the multiple processor cores at a time.
摘要翻译：一种包括包括多个处理器核心和应用的目标硬件的系统。该系统还包括通过连接耦合到目标硬件的主计算机，并适于通过经由连接接收跟踪信息来调试应用程序。在确定通过连接发送的跟踪信息时，目标硬件优先于由与令牌相关联的主处理器核心生成的跟踪信息优先于由与令牌不相关联的辅助处理器核心生成的跟踪信息。令牌每次与多个处理器内核之一相关联。

44. 发明申请

US20060294426A1 Read FIFO Scheduling for Multiple Streams While Maintaining Coherency 有权
标题翻译：在保持一致性的同时读取多个流的FIFO调度
公开(公告)号：US20060294426A1
公开(公告)日：2006-12-28
申请号：US11467683
申请日：2006-08-28
申请人： Manisha Agarwala , Maria Gill
发明人： Manisha Agarwala , Maria Gill
IPC分类号： G06F11/00
CPC分类号： G06F11/3636 , G06F11/3656
摘要： A method of scheduling trace packets in an integrated circuit generating trace packets of plural types stores trace data in respective first-in-first-out buffers. If a timing trace data first-in-first-out buffer is empty, timing trace data packet is transmitted. If a program counter overall data first-in-first-out buffer is not empty and the processor is at a data interruptible boundary, transmitting a program counter data packet. If data first-in-first-out buffer is not empty, transmitting a data packet. The program counter data packets include program counter sync data, program counter exception data, program counter relative branch data and program counter absolute branch data.
摘要翻译：一种在产生多种类型的跟踪分组的集成电路中调度跟踪分组的方法将跟踪数据存储在相应的先进先出缓冲器中。如果定时跟踪数据先进先出缓冲器为空，则发送定时跟踪数据包。如果程序计数器总数据先进先出缓冲器不为空并且处理器处于数据中断边界，则发送程序计数器数据包。如果数据先入先出缓冲区不为空，则发送数据包。程序计数器数据包包括程序计数器同步数据，程序计数器异常数据，程序计数器相对分支数据和程序计数器绝对分支数据。

45. 发明申请

US20060259751A1 MONITORING OF MEMORY AND EXTERNAL EVENTS 有权
标题翻译：监测记忆和外部事件
公开(公告)号：US20060259751A1
公开(公告)日：2006-11-16
申请号：US11383473
申请日：2006-05-15
申请人： Oliver Sohm , Gary Swoboda , Manisha Agarwala
发明人： Oliver Sohm , Gary Swoboda , Manisha Agarwala
IPC分类号： G06F9/44
CPC分类号： G06F9/3869
摘要： A system comprises a circuit configured to execute instructions and output event data corresponding to the execution of the instructions. The system also comprises a monitoring device coupled to the circuit. The monitoring device receives information about said event data. The event data comprises event data selected from a group consisting of memory events and external events.
摘要翻译：系统包括被配置为执行指令并输出与指令的执行相对应的事件数据的电路。该系统还包括耦合到该电路的监测装置。监视装置接收关于所述事件数据的信息。事件数据包括从由存储器事件和外部事件组成的组中选择的事件数据。

46. 发明申请

US20060255983A1 An Efficient Protocol for Encoding Software Pipelined Loop When PC Trace is Enabled 有权
标题翻译：当PC跟踪启用时，编码软件流水线循环的高效协议
公开(公告)号：US20060255983A1
公开(公告)日：2006-11-16
申请号：US11383636
申请日：2006-05-16
申请人： Manisha Agarwala
发明人： Manisha Agarwala
IPC分类号： H03M7/34
CPC分类号： G06F9/325 , G06F11/3636
摘要： A software pipeline loop (SPLOOP) is different from other discontinuities because it is repetitive. There are also other issues like the next iteration can start before the first one is complete. Furthermore, it is possible to reload it, and it may or may not be reloaded. It can terminate due to an exception. It can be drained in the middle for an interrupt. Once an SPLOOP becomes active, the PC stops advancing. While the SPLOOP is being loaded, certain instruction may or may not be executed, based on some specific conditions. The same is true for when the SPLOOP is draining.
摘要翻译：软件管道回路（SPLOOP）与其他不连续性不同，因为它是重复的。还有其他问题，如下一个迭代可以在第一个完成之前启动。此外，可以重新加载它，并且可以重新加载也可以不重新加载它。它可以由于异常终止。它可以在中间排出中断。一旦SPLOOP激活，PC停止前进。当SPLOOP正在加载时，某些指令可能会被执行，也可能不会被执行，基于一些具体的条件。当SPLOOP正在排水时也是如此。

47. 发明授权

US07133821B2 Read FIFO scheduling for multiple streams while maintaining coherency 有权
标题翻译：读取FIFO调度多个流，同时保持一致性
公开(公告)号：US07133821B2
公开(公告)日：2006-11-07
申请号：US10302191
申请日：2002-11-22
申请人： Manisha Agarwala , Maria B. H. Gill
发明人： Manisha Agarwala , Maria B. H. Gill
IPC分类号： G06F17/50 , G06F9/455 , G06F11/10
CPC分类号： G06F11/3636 , G06F11/3656
摘要： A method of scheduling trace packets in an integrated circuit generating trace packets of plural types stores trace data in respective first-in-first-out buffers. If a timing trace data first-in-first-out buffer is empty, timing trace data packet is transmitted. If a program counter overall data first-in-first-out buffer is not empty and the processor is at a data interruptible boundary, a program counter data packet is transmitted. If data first-in-first-out buffer is not empty, a data packet is transmitted. The program counter data packets include program counter sync data, program counter exception data, program counter relative branch data and program counter absolute branch data.
摘要翻译：一种在产生多种类型的跟踪分组的集成电路中调度跟踪分组的方法将跟踪数据存储在相应的先进先出缓冲器中。如果定时跟踪数据先进先出缓冲器为空，则发送定时跟踪数据包。如果程序计数器的总体数据先进先出缓冲器不为空并且处理器处于数据可中断边界，则发送程序计数器数据分组。如果数据先进先出缓冲器不为空，则传输数据包。程序计数器数据包包括程序计数器同步数据，程序计数器异常数据，程序计数器相对分支数据和程序计数器绝对分支数据。

48. 发明授权

US07127639B2 Distinguishing between two classes of trace information 有权
公开(公告)号：US07127639B2
公开(公告)日：2006-10-24
申请号：US10301968
申请日：2002-11-22
申请人： Manisha Agarwala
发明人： Manisha Agarwala
IPC分类号： G06F11/00
CPC分类号： G06F11/348
摘要： A method of tracing activity of a data processor generates a trace data stream during a normal background mode and a foreground mode while servicing a real time interrupt during an emulation halt. An Interrupt During Suspend bit is set in foreground modes and transmitted in the trace data stream to distinguish the trace data streams between background mode and foreground mode.

49. 发明授权

US07047178B2 Emulation pause and reset tracing of multiple sync points pointing to different addresses 有权
标题翻译：指向不同地址的多个同步点的仿真暂停和复位跟踪
公开(公告)号：US07047178B2
公开(公告)日：2006-05-16
申请号：US10301896
申请日：2002-11-22
申请人： Manisha Agarwala
发明人： Manisha Agarwala
IPC分类号： G06F9/455 , G06F9/45
CPC分类号： G06F11/3656 , G06F11/3636
摘要： A method of tracing data processor activity includes trace data markers indicating initiation and termination of at least one trace function at a specified program counter address and emulation pause related markers indicating initiation and termination of an emulation halt state at a specified program counter. Each emulation pause related marker includes a conflict bit indicating the presence or absence of a simultaneous trace data marker having a different program counter address.
摘要翻译：跟踪数据处理器活动的方法包括指示指定程序计数器地址处的至少一个跟踪功能的启动和终止的跟踪数据标记，以及指示指定程序计数器处的仿真停止状态的启动和终止的仿真暂停相关标记。每个仿真暂停相关标记包括指示存在或不存在具有不同程序计数器地址的同时跟踪数据标记的冲突位。

50. 发明授权

US5751162A Field programmable gate array logic module configurable as combinational or sequential circuits 失效
标题翻译：现场可编程门阵列逻辑模块可配置为组合或顺序电路
公开(公告)号：US5751162A
公开(公告)日：1998-05-12
申请号：US659990
申请日：1996-06-07
申请人： Mahesh Mehendale , Shivaling Mahant-Shetti , Manisha Agarwala , Mark G. Harward , Robert J. Landers
发明人： Mahesh Mehendale , Shivaling Mahant-Shetti , Manisha Agarwala , Mark G. Harward , Robert J. Landers
IPC分类号： H03K19/173
CPC分类号： H03K19/1737
摘要： A logic module 400 for use in a field programmable gate array 100 can be selectively reconfigured to perform over 2,200 boolean combinational functions on output 431, to operate as a full adder with sum and carry outputs, or to perform the sequential function of a D latch or a D flipflop. Logic module 400 is comprised of 2-input multiplexers 500 and 600 which are used to form both the combinational and sequential circuits, thereby efficiently utilizing space on gate array 100.
摘要翻译：可以选择性地重新配置用于现场可编程门阵列100的逻辑模块400，以在输出端431上执行2200多个布尔组合函数，以作为具有和和和进位输出的全加器运行，或执行D锁存器的顺序功能或D触发器。逻辑模块400由用于组合组合电路和顺序电路的2输入多路复用器500和600组成，从而有效利用门阵列100上的空间。

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