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41. 发明申请

US20070096319A1 Method for fabricating and BEOL interconnect structures with simultaneous formation of high-k and low-k dielectric regions 有权
标题翻译：同时形成高k和低k电介质区域的制造方法和BEOL互连结构
公开(公告)号：US20070096319A1
公开(公告)日：2007-05-03
申请号：US11266741
申请日：2005-11-03
申请人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
发明人： Louis Hsu , Jack Mandelman , William Tonti , Chih-Chao Yang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5329 , H01L21/7682 , H01L21/76849 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , Y10S438/942 , H01L2924/00
摘要： A method for fabricating and back-end-of-line (BEOL) metalization structures includes simultaneous high-k and low-k dielectric regions. An interconnect structure includes a first inter-level dielectric (ILD) layer and a second ILD layer with the first ILD layer underlying the second ILD layer. A plurality of columnar air gaps is formed in the first ILD. The columnar air gap structure is created using a two-phase photoresist material for providing different etching selectivity during subsequent processing.
摘要翻译：一种用于制造和后端（BEOL）金属化结构的方法包括同时存在的高k和低k电介质区域。互连结构包括第一层间电介质（ILD）层和具有位于第二ILD层下面的第一ILD层的第二ILD层。在第一ILD中形成多个柱状气隙。使用两相光致抗蚀剂材料制造柱状气隙结构，用于在随后的处理期间提供不同的蚀刻选择性。

42. 发明申请

US20070045697A1 Body-contacted semiconductor structures and methods of fabricating such body-contacted semiconductor structures 审中-公开
标题翻译：体接触半导体结构和制造这种体接触半导体结构的方法
公开(公告)号：US20070045697A1
公开(公告)日：2007-03-01
申请号：US11216386
申请日：2005-08-31
申请人： Kangguo Cheng , Louis Hsu , Jack Mandelman
发明人： Kangguo Cheng , Louis Hsu , Jack Mandelman
IPC分类号： H01L27/108
CPC分类号： H01L21/84 , H01L27/0218 , H01L27/10841 , H01L27/1203 , H01L29/66545
摘要： A semiconductor structure for a dynamic random access memory (DRAM) cell array that includes a plurality of vertical memory cells built on a semiconductor-on-insulator (SOI) wafer and a body contact in the buried dielectric layer of the SOI wafer. The body contact electrically couples a semiconductor body with a channel region of the access device of one vertical memory cell and a semiconductor substrate of the SOI wafer. The body contact provides a current leakage path that reduces the impact of floating body effects upon the vertical memory cell. The body contact may be formed by an ion implantation process that modifies the stoichiometry of a region of the buried dielectric layer so that the modified region becomes electrically conductive with a relatively high resistance.
摘要翻译：一种用于动态随机存取存储器（DRAM）单元阵列的半导体结构，其包括建立在绝缘体上半导体（SOI）晶片上的多个垂直存储单元和SOI晶片的埋入介质层中的体接触。体接触将半导体本体与一个垂直存储单元的存取器件的沟道区和SOI晶片的半导体衬底电耦合。身体接触提供了一种电流泄漏路径，可减少浮体对垂直记忆体的影响。体接触可以通过离子注入工艺形成，该方法改变掩埋介电层的区域的化学计量，使得改性区域以相对较高的电阻变为导电性。

43. 发明申请

US20070007601A1 Vertical MOSFET SRAM cell 审中-公开
标题翻译：垂直MOSFET SRAM单元
公开(公告)号：US20070007601A1
公开(公告)日：2007-01-11
申请号：US11509866
申请日：2006-08-25
申请人： Louis Hsu , Oleg Gluschenkov , Jack Mandelman , Carl Radens
发明人： Louis Hsu , Oleg Gluschenkov , Jack Mandelman , Carl Radens
IPC分类号： H01L21/8244 , H01L29/94 , H01L29/76
CPC分类号： H01L27/11 , G11C11/412 , H01L21/84 , H01L27/1104 , H01L27/1203
摘要： A method of forming an SRAM cell device includes the following steps. Form pass gate FET transistors and form a pair of vertical pull-down FET transistors with a first common body and a first common source in a silicon layer patterned into parallel islands formed on a planar insulator. Etch down through upper diffusions between cross-coupled inverter FET transistors to form pull-down isolation spaces bisecting the upper strata of pull-up and pull-down drain regions of the pair of vertical pull-down FET transistors, with the isolation spaces reaching down to the common body strata. Form a pair of vertical pull-up FET transistors with a second common body and a second common drain. Then, connect the FET transistors to form an SRAM cell.
摘要翻译：形成SRAM单元装置的方法包括以下步骤。形成栅极FET晶体管并形成一对垂直下拉FET晶体管，其具有第一共同体和第一公共源，图案化为形成在平面绝缘体上的平行岛的硅层。通过交叉耦合的反相器FET晶体管之间的上扩散来蚀刻，以形成将一对垂直下拉FET晶体管的上拉和下拉漏极区的上层平分的下拉隔离空间，隔离空间达到到共同的身体层。形成一对具有第二共同体和第二公共漏极的垂直上拉FET晶体管。然后，连接FET晶体管以形成SRAM单元。

44. 发明申请

US20060286781A1 Crystal imprinting methods for fabricating subsrates with thin active silicon layers 失效
标题翻译：用于制造具有薄的有源硅层的次级层的晶体压印方法
公开(公告)号：US20060286781A1
公开(公告)日：2006-12-21
申请号：US11154907
申请日：2005-06-16
申请人： Louis Hsu , Jack Mandelman , William Tonti
发明人： Louis Hsu , Jack Mandelman , William Tonti
IPC分类号： H01L21/00 , H01L21/20
CPC分类号： H01L29/045 , H01L21/84 , H01L27/1203
摘要： Methods of forming semiconductor structures characterized by a thin active silicon layer on an insulating substrate by a crystal imprinting or damascene approach. The methods include patterning an insulating layer to define a plurality of apertures, filling the apertures in the patterned insulating layer with amorphous silicon to define a plurality of amorphous silicon features, and re-growing the amorphous silicon features to define a thin active silicon layer consisting of regrown silicon features. The amorphous silicon features may be regrown such that a number have a first crystal orientation and another number have a different second crystal orientation.
摘要翻译：通过晶体压印或镶嵌法在绝缘基板上形成由活性硅层薄的特征的半导体结构的方法。所述方法包括图案化绝缘层以限定多个孔，用非晶硅填充图案化绝缘层中的孔以限定多个非晶硅特征，以及重新生长非晶硅特征以限定薄的有源硅层，的再生硅特征。可以重新生长非晶硅特征，使得数量具有第一晶体取向，而另一数目具有不同的第二晶体取向。

45. 发明申请

US20060189110A1 Body capacitor for SOI memory description 有权
标题翻译：用于SOI存储器描述的体电容
公开(公告)号：US20060189110A1
公开(公告)日：2006-08-24
申请号：US11064730
申请日：2005-02-24
申请人： Jack Mandelman , Louis Hsu , Rajiv Joshi
发明人： Jack Mandelman , Louis Hsu , Rajiv Joshi
IPC分类号： H01L21/3205
CPC分类号： H01L21/84 , H01L27/108 , H01L27/10832 , H01L27/10858 , H01L27/1203 , H01L29/94
摘要： A semiconductor structure having a body capacitance plate, which is formed with a process that assures that the body capacitance plate is self-aligned to both the source line (SL) diffusion and the bitline diffusion is provided. Thus the amount of overlap between the SL and the bitline diffusions and the body capacitance plate is precisely controlled. More specifically, the present invention forms the structure of a 1T-capacitorless SOI body charge storage cell having sidewall capacitor plates using a process that assures that there is 1) minimal overlap between plate and source/drain diffusions, and 2) that the minimal overlap obtained in the present invention is precisely controlled and is not subject to alignment tolerances. The inventive cell results in larger signal margin, improved performance, smaller chip size, and reduced dynamic power dissipation relative to the prior art.
摘要翻译：提供一种具有体电容板的半导体结构，其形成有确保体电容板与源极线（SL）扩散和位线扩散两者自对准的工艺。因此，SL和位线扩散和体电容板之间的重叠量被精确地控制。更具体地说，本发明通过使用确保存在1）板和源极/漏极扩散之间的最小重叠的过程形成具有侧壁电容器板的1T无电容的SOI体电荷存储单元的结构，以及2）最小重叠在本发明中获得的精确控制并且不受对准公差的影响。与现有技术相比，本发明的电池产生更大的信号余量，改善的性能，更小的芯片尺寸和降低的动态功耗。

46. 发明申请

US20050087814A1 Forming electronic structures having dual dielectric thicknesses and the structure so formed 失效
公开(公告)号：US20050087814A1
公开(公告)日：2005-04-28
申请号：US10995444
申请日：2004-11-23
申请人： Louis Hsu , Jack Mandelman , Carl Radens , Richard Strub , William Tonti
发明人： Louis Hsu , Jack Mandelman , Carl Radens , Richard Strub , William Tonti
IPC分类号： H01L21/8239 , H01L21/334 , H01L21/8234 , H01L21/8242 , H01L29/94 , H01L21/8238
CPC分类号： H01L29/66181 , H01L21/823462 , H01L27/10861 , H01L27/10894 , H01L29/945
摘要： A structure including a first device and a second device, wherein the second device has a dielectric thickness greater than the dielectric thickness of the first device, and the method of so forming the structure.

47. 发明申请

US20080064162A1 VERTICAL SOI TRANSISTOR MEMORY CELL AND METHOD OF FORMING THE SAME 失效
标题翻译：垂直SOI晶体管存储单元及其形成方法
公开(公告)号：US20080064162A1
公开(公告)日：2008-03-13
申请号：US11931238
申请日：2007-10-31
申请人： Kangguo Cheng , Jack Mandelman
发明人： Kangguo Cheng , Jack Mandelman
IPC分类号： H01L21/8242
CPC分类号： H01L27/1203 , H01L27/10841 , H01L27/10864
摘要： The present invention relates to a semiconductor device that contains at least one trench capacitor and at least one vertical transistor, and methods for forming such a semiconductor device. Specifically, the trench capacitor is located in a semiconductor substrate and comprises an outer electrode, an inner electrode, and a node dielectric layer located between the outer electrode and the inner electrode. The vertical transistor is located over the trench capacitor and comprises a source region, a drain region, a channel region, a gate dielectric, and a gate electrode. The channel region of the vertical transistor is located in a tensilely or compressively strained semiconductor layer that is oriented perpendicularly to a surface of the semiconductor substrate. Preferably, the tensilely or compressively strained semiconductor layer is embedded in an insulator structure, so that the vertical transistor has a semiconductor-on-insulator (SOI) configuration.
摘要翻译：本发明涉及包含至少一个沟槽电容器和至少一个垂直晶体管的半导体器件，以及用于形成这种半导体器件的方法。具体地，沟槽电容器位于半导体衬底中，并且包括外电极，内电极和位于外电极和内电极之间的节点电介质层。垂直晶体管位于沟槽电容器上方，并包括源极区，漏极区，沟道区，栅极电介质和栅电极。垂直晶体管的沟道区域位于垂直于半导体衬底的表面定向的拉伸或压缩应变的半导体层中。优选地，拉伸或压缩应变的半导体层嵌入绝缘体结构中，使得垂直晶体管具有绝缘体上半导体（SOI）构造。

48. 发明申请

US20080052659A1 Electrically Programmable pi-Shaped Fuse Structures and Design Process Therefore 失效
标题翻译：电可编程的pi形保险丝结构和设计过程
公开(公告)号：US20080052659A1
公开(公告)日：2008-02-28
申请号：US11923833
申请日：2007-10-25
申请人： Roger Booth , Kangguo Cheng , Jack Mandelman , William Tonti
发明人： Roger Booth , Kangguo Cheng , Jack Mandelman , William Tonti
IPC分类号： G06F17/50
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Electrically programmable fuses for an integrated circuit and design structures thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside over a first support and a second support, respectively, with the first support and the second support being spaced apart, and the fuse element bridging the distance between the first terminal portion over the first support and the second terminal portion over the second support. The fuse, first support and second support define a π-shaped structure in elevational cross-section through the fuse element. The first terminal portion, second terminal portion and fuse element are coplanar, with the fuse element residing above a void. The design structure for the fuse is embodied in a machine-readable medium for designing, manufacturing or testing a design of the fuse.
摘要翻译：提出了用于集成电路的电可编程保险丝及其设计结构，其中电可编程熔丝具有由熔丝元件互连的第一端子部分和第二端子部分。第一端子部分和第二端子部分分别驻留在第一支撑件和第二支撑件上，第一支撑件和第二支撑件间隔开，并且熔丝元件将第一端子部分之间的距离跨越第一支撑件和在第二支撑件上方的第二端子部分。保险丝，第一支撑件和第二支撑件通过保险丝元件在垂直截面中限定了一个pi形结构。第一端子部分，第二端子部分和熔丝元件是共面的，其中熔丝元件位于空隙之上。保险丝的设计结构体现在用于设计，制造或测试保险丝设计的机器可读介质中。

49. 发明申请

US20080042219A1 finFET Device 审中-公开
标题翻译： finFET器件
公开(公告)号：US20080042219A1
公开(公告)日：2008-02-21
申请号：US11923121
申请日：2007-10-24
申请人： Roger Booth , William Hovis , Jack Mandelman
发明人： Roger Booth , William Hovis , Jack Mandelman
IPC分类号： H01L29/94
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A finFET, a method of fabricating the finFET and a design structure of the finFET. The method includes: forming a silicon fin on a top surface of a silicon substrate; forming a gate dielectric on opposite sidewalls of the fin; forming a gate electrode over a channel region of the fin, the gate electrode in direct physical contact with the gate dielectric layer on the opposite sidewalls of the fin; forming a first source/drain in the fin on a first side of the channel region and forming a second source/drain in the fin on a second side of the channel region; removing a portion of the substrate from under at least a portion of the first and second source/drains to create a void; and filling the void with a dielectric material. The finFET includes a body contact between the silicon body of the finFET and the substrate.
摘要翻译： finFET，finFET的制造方法以及finFET的设计结构。该方法包括：在硅衬底的顶表面上形成硅翅片; 在翅片的相对侧壁上形成栅电介质; 在鳍片的沟道区域上形成栅电极，栅电极与翅片的相对侧壁上的栅介电层直接物理接触; 在所述通道区域的第一侧上在所述翅片中形成第一源极/漏极，并且在所述沟道区域的第二侧上在所述鳍片中形成第二源极/漏极; 从第一和第二源/排水沟的至少一部分下方去除衬底的一部分以产生空隙; 并用介电材料填充空隙。 finFET包括在finFET的硅体和衬底之间的体接触。

50. 发明申请

US20080042204A1 METHODS FOR FABRICATING A SEMICONDUCTOR STRUCTURE USING A MANDREL AND SEMICONDUCTOR STRUCTURES FORMED THEREBY 审中-公开
公开(公告)号：US20080042204A1
公开(公告)日：2008-02-21
申请号：US11924875
申请日：2007-10-26
申请人： Kangguo Cheng , Jack Mandelman
发明人： Kangguo Cheng , Jack Mandelman
IPC分类号： H01L27/12
CPC分类号： H01L29/785 , H01L29/66795
摘要： Methods of fabricating a semiconductor structure in which a body of monocrystalline silicon is formed on a sidewall of a sacrificial mandrel and semiconductor structures made by the methods. After the body of monocrystalline silicon is formed, the sacrificial material of the mandrel is removed selective to the monocrystalline silicon of the body. The mandrel may be composed of porous silicon and the body may be fabricated using either a semiconductor-on-insulator substrate or a bulk substrate. The body may be used to fabricate a fin body of a fin-type field effect transistor.

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