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41. 发明授权

US07528493B2 Interconnect structure and method of fabrication of same 有权
标题翻译：互连结构及其制造方法
公开(公告)号：US07528493B2
公开(公告)日：2009-05-05
申请号：US11860590
申请日：2007-09-25
申请人： Chih-Chao Yang , Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Meeyoung H. Yoon
发明人： Chih-Chao Yang , Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Meeyoung H. Yoon
IPC分类号： H01L29/06 , H01L21/4763
CPC分类号： H01L21/76849 , H01L21/76807 , H01L21/76814 , H01L21/76831 , H01L21/76843 , H01L2924/0002 , H01L2924/00
摘要： A damascene wire and method of forming the wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing the sidewalls of the trench under the mask layer; forming a conformal conductive liner on all exposed surface of the trench and the mask layer; filling the trench with a core electrical conductor; removing portions of the conductive liner extending above the top surface of the dielectric layer and removing the mask layer; and forming a conductive cap on a top surface of the core conductor. The structure includes a core conductor clad in a conductive liner and a conductive capping layer in contact with the top surface of the core conductor that is not covered by the conductive liner.
摘要翻译：一种镶嵌线及其形成方法。该方法包括：在电介质层的顶表面上形成掩模层; 在掩模层中形成开口; 在电介质层中形成沟槽，其中电介质层不被掩模层保护; 使掩模层下方的沟槽的侧壁凹陷; 在沟槽和掩模层的所有暴露表面上形成共形导电衬垫; 用芯电导体填充沟槽; 去除在电介质层的顶表面上方延伸的导电衬垫的部分，并去除掩模层; 以及在所述芯导体的顶表面上形成导电帽。该结构包括包覆在导电衬垫中的芯导体和与未被导电衬垫覆盖的芯导体的顶表面接触的导电覆盖层。

42. 发明授权

US07402463B2 Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application 有权
标题翻译：采用埋入导电层的特征，用于电抗保险丝应用的电介质
公开(公告)号：US07402463B2
公开(公告)日：2008-07-22
申请号：US11207218
申请日：2005-08-19
申请人： Chih-Chao Yang , Lawrence A. Clevenger , Timothy J. Dalton , Nicholas C. Fuller , Louis C. Hsu
发明人： Chih-Chao Yang , Lawrence A. Clevenger , Timothy J. Dalton , Nicholas C. Fuller , Louis C. Hsu
IPC分类号： H01L21/82
CPC分类号： H01L23/5252 , H01L21/76843 , H01L21/76844 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure comprises regions of leaky dielectric between interconnects. The resistance between these original interconnects starts decreasing when two adjacent interconnects are biased and causes a time-dependent dielectric breakdown, TDDB, phenomenon to occur. Decreasing of the resistance between adjacent interconnects can also be expedited via increasing the local temperature.
摘要翻译：提供了一种抗熔丝结构，其包括掩埋的导电的，例如作为反熔丝材料的金属层以及形成这种抗熔丝结构的方法。根据本发明，本发明的抗熔丝结构包括互连之间的漏电介质区域。当两个相邻的互连被偏置时，这些原始互连之间的电阻开始减小，并且引起时间依赖介质击穿TDDB现象。也可以通过增加局部温度来加速相邻互连之间的电阻的降低。

43. 发明授权

US07335588B2 Interconnect structure and method of fabrication of same 失效
标题翻译：互连结构及其制造方法
公开(公告)号：US07335588B2
公开(公告)日：2008-02-26
申请号：US11107074
申请日：2005-04-15
申请人： Chih-Chao Yang , Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Meeyoung H. Yoon
发明人： Chih-Chao Yang , Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Meeyoung H. Yoon
IPC分类号： H01L24/4763
CPC分类号： H01L21/76849 , H01L21/76807 , H01L21/76814 , H01L21/76831 , H01L21/76843 , H01L2924/0002 , H01L2924/00
摘要： A damascene wire and method of forming the wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing the sidewalls of the trench under the mask layer; forming a conformal conductive liner on all exposed surface of the trench and the mask layer; filling the trench with a core electrical conductor; removing portions of the conductive liner extending above the top surface of the dielectric layer and removing the mask layer; and forming a conductive cap on a top surface of the core conductor. The structure includes a core conductor clad in a conductive liner and a conductive capping layer in contact with the top surface of the core conductor that is not covered by the conductive liner.
摘要翻译：一种镶嵌线及其形成方法。该方法包括：在电介质层的顶表面上形成掩模层; 在掩模层中形成开口; 在电介质层中形成沟槽，其中电介质层不被掩模层保护; 使掩模层下方的沟槽的侧壁凹陷; 在沟槽和掩模层的所有暴露表面上形成共形导电衬垫; 用芯电导体填充沟槽; 去除在电介质层的顶表面上方延伸的导电衬垫的部分，并去除掩模层; 以及在所述芯导体的顶表面上形成导电帽。该结构包括包覆在导电衬垫中的芯导体和与未被导电衬垫覆盖的芯导体的顶表面接触的导电覆盖层。

44. 发明授权

US07223654B2 MIM capacitor and method of fabricating same 有权
标题翻译： MIM电容器及其制造方法
公开(公告)号：US07223654B2
公开(公告)日：2007-05-29
申请号：US11106887
申请日：2005-04-15
申请人： Chih-Chao Yang , Lawrence A. Clevenger , Timothy J. Dalton , Louis C. Hsu
发明人： Chih-Chao Yang , Lawrence A. Clevenger , Timothy J. Dalton , Louis C. Hsu
IPC分类号： H01L21/8242 , H01L21/20
CPC分类号： H01L23/5223 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A damascene MIM capacitor and a method of fabricating the MIM capacitor. The MIN capacitor includes a dielectric layer having top and bottom surfaces; a trench in the dielectric layer, the trench extending from the top surface to the bottom surface of the dielectric layer; a first plate of a MIM capacitor comprising a conformal conductive liner formed on all sidewalls and extending along a bottom of the trench, the bottom of the trench coplanar with the bottom surface of the dielectric layer; an insulating layer formed over a top surface of the conformal conductive liner; and a second plate of the MIM capacitor comprising a core conductor in direct physical contact with the insulating layer, the core conductor filling spaces in the trench not filled by the conformal conductive liner and the insulating layer. The method includes forming portions of the MIM capacitor simultaneously with damascene interconnection wires.
摘要翻译：一种镶嵌MIM电容器和一种制造MIM电容器的方法。 MIN电容器包括具有顶表面和底表面的电介质层; 电介质层中的沟槽，沟槽从电介质层的顶表面延伸到底表面; MIM电容器的第一板包括形成在所有侧壁上并沿着沟槽的底部延伸的共形导电衬垫，沟槽的底部与电介质层的底表面共面; 绝缘层，形成在所述共形导电衬垫的顶表面上; 以及MIM电容器的第二板，其包括与所述绝缘层直接物理接触的芯导体，所述芯导体填充所述沟槽中的未被所述共形导电衬垫和所述绝缘层填充的空间。该方法包括与镶嵌互连线同时形成MIM电容器的部分。

45. 发明授权

US08159042B2 Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application 有权
标题翻译：采用埋入导电层的特征，用于电抗保险丝应用的电介质
公开(公告)号：US08159042B2
公开(公告)日：2012-04-17
申请号：US12144229
申请日：2008-06-23
申请人： Chih-Chao Yang , Lawrence A. Clevenger , Timothy J. Dalton , Nicholas C. Fuller , Louis C. Hsu
发明人： Chih-Chao Yang , Lawrence A. Clevenger , Timothy J. Dalton , Nicholas C. Fuller , Louis C. Hsu
IPC分类号： H01L23/52
CPC分类号： H01L23/5252 , H01L21/76843 , H01L21/76844 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse structure that included a buried electrically conductive, e.g., metallic layer as an anti-fuse material as well as a method of forming such an anti-fuse structure are provided. According to the present invention, the inventive anti-fuse structure comprises regions of leaky dielectric between interconnects. The resistance between these original interconnects starts decreasing when two adjacent interconnects are biased and causes a time-dependent dielectric breakdown, TDDB, phenomenon to occur. Decreasing of the resistance between adjacent interconnects can also be expedited via increasing the local temperature.
摘要翻译：提供了一种抗熔丝结构，其包括掩埋的导电的，例如作为反熔丝材料的金属层以及形成这种抗熔丝结构的方法。根据本发明，本发明的抗熔丝结构包括互连之间的漏电介质区域。当两个相邻的互连被偏置时，这些原始互连之间的电阻开始减小，并且引起时间依赖介质击穿TDDB现象。也可以通过增加局部温度来加速相邻互连之间的电阻的降低。

46. 发明授权

US07494915B2 Back end interconnect with a shaped interface 失效
标题翻译：后端互连与成形接口
公开(公告)号：US07494915B2
公开(公告)日：2009-02-24
申请号：US11463447
申请日：2006-08-09
申请人： Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Mark Hoinkis , Steffen K. Kaldor , Erdem Kaltalioglu , Kaushik A. Kumar , Douglas C. La Tulipe, Jr. , Jochen Schacht , Andrew H. Simon , Terry A. Spooner , Yun-Yu Wang , Clement H. Wann , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Mark Hoinkis , Steffen K. Kaldor , Erdem Kaltalioglu , Kaushik A. Kumar , Douglas C. La Tulipe, Jr. , Jochen Schacht , Andrew H. Simon , Terry A. Spooner , Yun-Yu Wang , Clement H. Wann , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76807 , H01L21/76814 , H01L21/76846 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.
摘要翻译：在集成电路的线的后端中的互连结构通过在锥形孔中去除下互连的顶表面中的材料而形成连续层之间的接触，该去除过程延伸穿过上孔的衬垫，以及沉积向下延伸到锥形孔中的第二衬垫，从而增加接触件的机械强度，从而提高集成电路的整体可靠性。

47. 发明授权

US07488677B2 Interconnect structures with encasing cap and methods of making thereof 失效
标题翻译：具有封盖的互连结构及其制造方法
公开(公告)号：US07488677B2
公开(公告)日：2009-02-10
申请号：US11503259
申请日：2006-08-14
申请人： Kwong Hon Wong , Louis C. Hsu , Timothy J. Dalton , Carol Radens , Chih-Chao Yang , Lawrence A. Clevenger , Theodorus E. Standaert
发明人： Kwong Hon Wong , Louis C. Hsu , Timothy J. Dalton , Carol Radens , Chih-Chao Yang , Lawrence A. Clevenger , Theodorus E. Standaert
IPC分类号： H01L21/4763
CPC分类号： H01L21/76852 , H01L21/288 , H01L21/2885 , H01L21/76885 , H01L23/5226 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of making an interconnect that includes providing an interconnect structure in a dielectric material, recessing the dielectric material such that a portion of the interconnect structure extends above an upper surface of the dielectric; and depositing an encasing cap over the extended portion of the interconnect structure.
摘要翻译：一种制造互连的方法，包括在电介质材料中提供互连结构，使电介质材料凹陷，使得互连结构的一部分在电介质的上表面上方延伸; 以及在所述互连结构的延伸部分上沉积封装盖。

48. 发明申请

US20080246151A1 INTERCONNECT STRUCTURE AND METHOD OF FABRICATION OF SAME 失效
公开(公告)号：US20080246151A1
公开(公告)日：2008-10-09
申请号：US12140352
申请日：2008-06-17
申请人： Chih-Chao Yang , Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Meeyoung H. Yoon
发明人： Chih-Chao Yang , Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Meeyoung H. Yoon
IPC分类号： H01L23/52
CPC分类号： H01L21/76849 , H01L21/76807 , H01L21/76814 , H01L21/76831 , H01L21/76843 , H01L2924/0002 , H01L2924/00
摘要： A damascene wire and method of forming the wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing the sidewalls of the trench under the mask layer; forming a conformal conductive liner on all exposed surface of the trench and the mask layer; filling the trench with a core electrical conductor; removing portions of the conductive liner extending above the top surface of the dielectric layer and removing the mask layer; and forming a conductive cap on a top surface of the core conductor. The structure includes a core conductor clad in a conductive liner and a conductive capping layer in contact with the top surface of the core conductor that is not covered by the conductive liner.

49. 发明授权

US07122462B2 Back end interconnect with a shaped interface 有权
公开(公告)号：US07122462B2
公开(公告)日：2006-10-17
申请号：US10707122
申请日：2003-11-21
申请人： Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Mark Hoinkis , Steffen K. Kaldor , Erdem Kaltalioglu , Kaushik A. Kumar , Douglas C. La Tulipe, Jr. , Jochen Schacht , Andrew H. Simon , Terry A. Spooner , Yun-Yu Wang , Clement H. Wann , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Mark Hoinkis , Steffen K. Kaldor , Erdem Kaltalioglu , Kaushik A. Kumar , Douglas C. La Tulipe, Jr. , Jochen Schacht , Andrew H. Simon , Terry A. Spooner , Yun-Yu Wang , Clement H. Wann , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76807 , H01L21/76814 , H01L21/76846 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.

50. 发明授权

US07906428B2 Modified via bottom structure for reliability enhancement 有权
标题翻译：通过底部结构改进可靠性增强
公开(公告)号：US07906428B2
公开(公告)日：2011-03-15
申请号：US12121216
申请日：2008-05-15
申请人： Lawrence A. Clevenger , Timothy Joseph Dalton , Louis C. Hsu , Conal Eugene Murray , Carl Radens , Kwong-Hon Wong , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Timothy Joseph Dalton , Louis C. Hsu , Conal Eugene Murray , Carl Radens , Kwong-Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/76805 , H01L21/76843 , H01L21/76844 , H01L21/76847 , H01L21/76865 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The present invention provides an interconnect structure that can be made in the BEOL which exhibits good mechanical contact during normal chip operations and does not fail during various reliability tests as compared with the conventional interconnect structures described above. The inventive interconnect structure has a kinked interface at the bottom of a via that is located within an interlayer dielectric layer. Specifically, the inventive interconnect structure includes a first dielectric layer having at least one metallic interconnect embedded within a surface thereof; a second dielectric layer located atop the first dielectric layer, wherein said second dielectric layer has at least one aperture having an upper line region and a lower via region, wherein the lower via region includes a kinked interface; at least one pair of liners located on at least vertical walls of the at least one aperture; and a conductive material filling the at least one aperture.
摘要翻译：本发明提供一种可以在BEOL中制造的互连结构，其在正常的芯片操作期间表现出良好的机械接触，并且在与上述的常规互连结构相比在各种可靠性测试期间不会失败。本发明的互连结构在通孔的底部具有位于层间介质层内的扭结界面。具体地，本发明的互连结构包括：第一介电层，其具有嵌入在其表面内的至少一个金属互连; 位于所述第一介电层顶部的第二电介质层，其中所述第二电介质层具有至少一个具有上线区域和下通孔区域的孔，其中所述下通孔区域包括扭结界面; 位于所述至少一个孔的至少垂直壁上的至少一对衬垫; 以及填充所述至少一个孔的导电材料。

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