会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 44. 发明授权
    • Information encoding method and apparatus, and information decoding
method and apparatus
    • 信息编码方法和装置,以及信息解码方法和装置
    • US5754127A
    • 1998-05-19
    • US530319
    • 1995-09-27
    • Kyoya TsutsuiMito Sonohara
    • Kyoya TsutsuiMito Sonohara
    • H04B1/66H03M5/22
    • H04B1/667G10L25/18
    • In this invention, in the case of transforming an input waveform signal into frequency components at a frequency component decomposing circuit 701 to allow the frequency components from the frequency component decomposing circuit 701 to undergo normalization and quantization, and encoding at a normalizing/quantizing circuit 702 and a code train generating circuit 703, operation of QMF is omitted with respect to bands of the unnecessary side by a processing band control circuit 704, whereby the number of operations necessary for filter operation is reduced so that high speed operation can be carried out and work area necessary for filter operation can be reduced. Namely, this invention can simplify filter operation in accordance with, e.g., required quality of reproduction signal, and can reduce circuit scale of encoding unit/decoding unit.
    • PCT No.PCT / JP95 / 00154 Sec。 371日期1995年9月27日第 102(e)1995年9月27日PCT PCT 1995年2月6日PCT公布。 公开号WO95 / 21490 日期1995年8月10日在本发明中,在将输入波形信号变换为频率分量分解电路701的频率成分的情况下,使来自频率分量分解电路701的频率成分进行归一化和量化, 归一化/量化电路702和码串发生电路703,由处理频带控制电路704相对于不需要的频带的频带省略了QMF的操作,从而降低了滤波器操作所需的操作次数,使得高速操作 可以进行过滤操作所需的工作区域。 也就是说,本发明可以根据例如再现信号的所需质量来简化滤波器操作,并且可以减少编码单元/解码单元的电路规模。
    • 45. 发明授权
    • Information encoding method and apparatus, information decoding method
and apparatus information transmission method and information recording
medium
    • 信息编码方法和装置,信息解码方法和装置信息传输方法以及信息记录介质
    • US5752224A
    • 1998-05-12
    • US868665
    • 1997-06-04
    • Kyoya TsutsuiRobert Heddle
    • Kyoya TsutsuiRobert Heddle
    • G11B20/10G10L19/00G10L19/02G10L19/08H03M7/30H04B1/66H04B14/04G10L3/00
    • G10L19/035
    • An information encoding method and apparatus, an information decoding method and apparatus and an information transmission method in which encoding and decoding with higher efficiency and higher sound quality may be achieved by gain control in meeting with the degree of amplitude changes in the attack portion and the pre-echo may be prevented from occurring. Gain control and gain control compensation operations are performed by applying a gain control function with a smaller gain control quantity and by applying a gain control function with a larger gain control quantity to a signal waveform portion having a level just ahead of an attack portion higher than a pre-set level and to a signal waveform portion having an extremely low level just ahead of the attack portion, respectively. By changing the gain control quantity depending on the degree of amplitude changes at the attack portion of the signal waveform, the pre-echo is prevented from occurring, while the efficiency is prevented from being lowered due to energy diffusion in the frequency domain.
    • 一种信息编码方法和装置,信息解码方法和装置以及信息传输方法,其中可以通过增益控制来实现更高效率和更高音质的编码和解码,以满足攻击部分和 可以防止发生前回波。 增益控制和增益控制补偿操作通过应用具有较小增益控制量的增益控制功能并且通过将具有较大增益控制量的增益控制功能应用于具有高于 预设电平和信号波形部分分别具有在攻击部分之前的极低电平。 通过根据信号波形的发生部分的振幅变化程度来改变增益控制量,防止了由于频域中的能量扩散而导致的效率被降低。
    • 47. 发明授权
    • Modified discrete cosine transform signal transforming system
    • 改进的离散余弦变换信号变换系统
    • US5640421A
    • 1997-06-17
    • US731698
    • 1996-10-17
    • Mito SonoharaKyoya Tsutsui
    • Mito SonoharaKyoya Tsutsui
    • H04B14/00G06F17/14A04B14/00
    • G06F17/147
    • An MDCT calculating circuit includes an x.sub.01 calculating circuit for multiplying input signals with a forward transforming window and a linear forward transforming unit for linear forward transforming an output signal of the calculating circuit. The linear forward transforming unit includes an x.sub.02 calculating circuit and an x.sub.03 calculating circuit for pre-processing the output signal of the x.sub.01 calculating circuit and an integration and summation processing circuit for executing integration and summation processing operations on an output signal of the pre-processing unit. The integration and summation processing circuit executes an integration and summation operation on an N/2 number of input signals from the pre-processing unit by grouping a k number of input signals as a processing unit and iteratively executes the integration and summation processing operations a N/(2*K) number of times for outputting a sum total of N/2 number of signals.
    • MDCT计算电路包括用于将输入信号与正向变换窗口相乘的x01计算电路和用于对计算电路的输出信号进行线性正向变换的线性正向变换单元。 线性正向变换单元包括x02计算电路和用于预处理x01计算电路的输出信号的x03计算电路和用于对预处理的输出信号执行积分和求和处理电路的积分和求和处理电路 单元。 积分和求和处理电路对来自预处理单元的N / 2数量的输入信号执行积分和求和操作,通过将输入信号的ak个数量分组为一个处理单元,并迭代地执行积分和求和处理操作N / (2 * K)次数输出N / 2个信号的总数。
    • 48. 发明授权
    • Method and apparatus for data encoding and data recording medium
    • 用于数据编码和数据记录介质的方法和设备
    • US5623557A
    • 1997-04-22
    • US413395
    • 1995-03-30
    • Osamu ShimoyoshiMito SonoharaKyoya Tsutsui
    • Osamu ShimoyoshiMito SonoharaKyoya Tsutsui
    • G11B20/10G10L19/00G10L19/02G11B20/00H03M7/30H03M7/40H04B1/66G06K9/00
    • H04B1/667G11B20/00007
    • A data encoding method apparatus in which the volume of arithmetic-logical operations for calculating the total number of bits required for encoding for adaptive bit allocation in the variable length encoding system for expediting the processing. In the data encoding apparatus for encoding and subsequently variable length encoding the input data, spectral data obtained on orthogonal transform coding are routed to a block floating circuit 403 for normalization and re-quantized in a quantization circuit 404 depending on the bit allocation number information from a bit allocation calculating circuit 406 so as to be then variable length encoded by an encoding circuit 407 and outputted at an output terminal 408. The bit allocation circuit 406 refers to a table memory circuit 409 in which re-quantized data domain is divided at boundary points corresponding to code length transitions in order to calculate the total number of bits required for encoding using a smaller volume of arithmetic-logical operations for the purpose of adjusting the number of allocated bits.
    • 一种数据编码方法装置,其中用于计算可变长度编码系统中的自适应位分配的编码所需的总位数的算术运算量用于加速处理。 在用于编码的数据编码装置和随后的可变长度编码输入数据中,在正交变换编码中获得的频谱数据被路由到块浮动电路403,以便在量化电路404中进行归一化和重新量化,这取决于来自 比特分配计算电路406,由编码电路407进行可变长度编码,并在输出端408输出。比特分配电路406参考其中重新量化的数据域被划分为边界的表存储器电路409 对应于代码长度转换的点,以便为了调整分配的位数而计算使用较小量的算术逻辑运算进行编码所需的总位数。