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41. 发明授权

US07498647B2 Packaged microelectronic imagers and methods of packaging microelectronic imagers 有权
标题翻译：封装的微电子成像器和包装微电子成像器的方法
公开(公告)号：US07498647B2
公开(公告)日：2009-03-03
申请号：US10864974
申请日：2004-06-10
申请人： Kyle K. Kirby , Salman Akram , William M. Hiatt
发明人： Kyle K. Kirby , Salman Akram , William M. Hiatt
IPC分类号： H01L21/00
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/48 , H01L27/14618 , H01L27/14625 , H01L31/0203 , H01L31/02325 , H01L2224/48227 , H01L2924/00014 , H01L2924/01029 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/04941 , H01L2924/12042 , H01L2924/14 , H01L2924/15174 , H04N5/2257 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging die can include a microelectronic substrate, an integrated circuit, and an image sensor electrically coupled to the integrated circuit. A bond-pad is carried by the substrate and electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends partially through the substrate and is in contact with the bond-pad. The interconnect can include a passage extending partially through the substrate to the bond-pad, a dielectric liner deposited into the passage and in contact with the substrate, a conductive layer deposited onto at least a portion of the dielectric liner, a wetting agent deposited onto at least a portion of the conductive layer, and a conductive fill material deposited into the passage and electrically coupled to the bond-pad.
摘要翻译：本文公开了微电子成像器，用于封装微电子成像器的方法，以及用于在微电子成像器中形成导电晶片间互连的方法。在一个实施例中，微电子成像管芯可以包括微电子衬底，集成电路和电耦合到集成电路的图像传感器。接合焊盘由衬底承载并电耦合到集成电路。导电晶片互连部分地穿过衬底延伸并与焊盘接触。互连可以包括部分地延伸穿过衬底到接合焊盘的通道，沉积到通道中并与衬底接触的介电衬垫，沉积在电介质衬垫的至少一部分上的导电层，沉积在电介质衬垫上的润湿剂所述导电层的至少一部分以及沉积到所述通道中并电耦合到所述接合焊盘的导电填充材料。

42. 发明授权

US08703518B2 Packaged microelectronic imagers and methods of packaging microelectronic imagers 有权
标题翻译：封装的微电子成像器和包装微电子成像器的方法
公开(公告)号：US08703518B2
公开(公告)日：2014-04-22
申请号：US13236907
申请日：2011-09-20
申请人： Kyle K. Kirby , Salman Akram , William M. Hiatt
发明人： Kyle K. Kirby , Salman Akram , William M. Hiatt
IPC分类号： H01L21/60 , H01L31/18 , H01L31/0224
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/48 , H01L27/14618 , H01L27/14625 , H01L31/0203 , H01L31/02325 , H01L2224/48227 , H01L2924/00014 , H01L2924/01029 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/04941 , H01L2924/12042 , H01L2924/14 , H01L2924/15174 , H04N5/2257 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging die can include a microelectronic substrate, an integrated circuit, and an image sensor electrically coupled to the integrated circuit. A bond-pad is carried by the substrate and electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends partially through the substrate and is in contact with the bond-pad. The interconnect can include a passage extending partially through the substrate to the bond-pad, a dielectric liner deposited into the passage and in contact with the substrate, a conductive layer deposited onto at least a portion of the dielectric liner, a wetting agent deposited onto at least a portion of the conductive layer, and a conductive fill material deposited into the passage and electrically coupled to the bond-pad.
摘要翻译：本文公开了微电子成像器，用于封装微电子成像器的方法，以及用于在微电子成像器中形成导电晶片间互连的方法。在一个实施例中，微电子成像管芯可以包括微电子衬底，集成电路和电耦合到集成电路的图像传感器。接合焊盘由衬底承载并电耦合到集成电路。导电晶片互连部分地穿过衬底延伸并与焊盘接触。互连可以包括部分地延伸穿过衬底到接合焊盘的通道，沉积到通道中并与衬底接触的介电衬垫，沉积在电介质衬垫的至少一部分上的导电层，沉积在电介质衬垫上的润湿剂所述导电层的至少一部分以及沉积到所述通道中并电耦合到所述接合焊盘的导电填充材料。

43. 发明申请

US20120009717A1 PACKAGED MICROELECTRONIC IMAGERS AND METHODS OF PACKAGING MICROELECTRONIC IMAGERS 有权
标题翻译：包装微电子图像和包装微电子图像的方法
公开(公告)号：US20120009717A1
公开(公告)日：2012-01-12
申请号：US13236907
申请日：2011-09-20
申请人： Kyle K. Kirby , Salman Akram , William M. Hiatt
发明人： Kyle K. Kirby , Salman Akram , William M. Hiatt
IPC分类号： H01L31/0224
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/48 , H01L27/14618 , H01L27/14625 , H01L31/0203 , H01L31/02325 , H01L2224/48227 , H01L2924/00014 , H01L2924/01029 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/04941 , H01L2924/12042 , H01L2924/14 , H01L2924/15174 , H04N5/2257 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging die can include a microelectronic substrate, an integrated circuit, and an image sensor electrically coupled to the integrated circuit. A bond-pad is carried by the substrate and electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends partially through the substrate and is in contact with the bond-pad. The interconnect can include a passage extending partially through the substrate to the bond-pad, a dielectric liner deposited into the passage and in contact with the substrate, a conductive layer deposited onto at least a portion of the dielectric liner, a wetting agent deposited onto at least a portion of the conductive layer, and a conductive fill material deposited into the passage and electrically coupled to the bond-pad.
摘要翻译：本文公开了微电子成像器，用于封装微电子成像器的方法，以及用于在微电子成像器中形成导电晶片间互连的方法。在一个实施例中，微电子成像管芯可以包括微电子衬底，集成电路和电耦合到集成电路的图像传感器。接合焊盘由衬底承载并电耦合到集成电路。导电晶片互连部分地穿过衬底延伸并与焊盘接触。互连可以包括部分地延伸穿过衬底到接合焊盘的通道，沉积到通道中并与衬底接触的介电衬垫，沉积在电介质衬垫的至少一部分上的导电层，沉积在电介质衬垫上的润湿剂所述导电层的至少一部分以及沉积到所述通道中并电耦合到所述接合焊盘的导电填充材料。

44. 发明授权

US07858429B2 Packaged microelectronic imagers and methods of packaging microelectronic imagers 有权
标题翻译：封装的微电子成像器和包装微电子成像器的方法
公开(公告)号：US07858429B2
公开(公告)日：2010-12-28
申请号：US11863087
申请日：2007-09-27
申请人： Salman Akram , Charles M. Watkins , Kyle K. Kirby , Alan G. Wood , William M. Hiatt
发明人： Salman Akram , Charles M. Watkins , Kyle K. Kirby , Alan G. Wood , William M. Hiatt
IPC分类号： H01L21/00 , G02F1/13
CPC分类号： H01L27/146 , H01L21/76898 , H01L27/14618 , H01L27/148 , H01L31/02016 , H01L2224/48227 , H01L2924/01046 , H01L2924/01066 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/00
摘要： Microelectronic imagers, methods for packaging microelectronic imagers, and methods for forming electrically conductive through-wafer interconnects in microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging die can include a microelectronic substrate, an integrated circuit, and an image sensor electrically coupled to the integrated circuit. A bond-pad is carried by the substrate and electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends through the substrate and is in contact with the bond-pad. The interconnect can include a passage extending completely through the substrate and the bond-pad, a dielectric liner deposited into the passage and in contact with the substrate, first and second conductive layers deposited onto at least a portion of the dielectric liner, and a conductive fill material deposited into the passage over at least a portion of the second conductive layer and electrically coupled to the bond-pad.
摘要翻译：本文公开了微电子成像器，用于封装微电子成像器的方法，以及用于在微电子成像器中形成导电晶片间互连的方法。在一个实施例中，微电子成像管芯可以包括微电子衬底，集成电路和电耦合到集成电路的图像传感器。接合焊盘由衬底承载并电耦合到集成电路。导电晶片互连延伸穿过衬底并与接合焊盘接触。互连可以包括完全延伸穿过衬底和接合焊盘的通道，沉积到通道中并与衬底接触的电介质衬垫，沉积在电介质衬垫的至少一部分上的第一和第二导电层以及导电在第二导电层的至少一部分上沉积到通道中并且电耦合到接合焊盘的填充材料。

45. 发明授权

US07148715B2 Systems and methods for testing microelectronic imagers and microfeature devices 有权
公开(公告)号：US07148715B2
公开(公告)日：2006-12-12
申请号：US10860699
申请日：2004-06-02
申请人： Salman Akram , William M. Hiatt , Alan G. Wood , Charles M. Watkins , Kyle K. Kirby
发明人： Salman Akram , William M. Hiatt , Alan G. Wood , Charles M. Watkins , Kyle K. Kirby
IPC分类号： G01R31/02 , G01R31/26 , H01L27/00
CPC分类号： G01R31/2635 , G01R31/2831
摘要： Systems and methods for testing microelectronic imagers and microfeature devices are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece including a substrate having a front side, a backside, and a plurality of microelectronic dies. The individual dies include an integrated circuit and a plurality of contact pads at the backside of the substrate operatively coupled to the integrated circuit. The method includes contacting individual contact pads with corresponding pins of a probe card. The method further includes testing the dies. In another embodiment, the individual dies can further comprise an image sensor at the front side of the substrate and operatively coupled to the integrated circuit. The image sensors are illuminated while the dies are tested.

46. 发明授权

US07250780B2 Probe card for semiconductor wafers having mounting plate and socket 失效
标题翻译：带安装板和插座的半导体晶圆探头卡
公开(公告)号：US07250780B2
公开(公告)日：2007-07-31
申请号：US10742729
申请日：2003-12-19
申请人： David R. Hembree , Warren M. Farnworth , Salman Akram , Alan G. Wood , C. Patrick Doherty , Andrew J. Krivy
发明人： David R. Hembree , Warren M. Farnworth , Salman Akram , Alan G. Wood , C. Patrick Doherty , Andrew J. Krivy
IPC分类号： G01R1/073 , G01R31/28
CPC分类号： G01R31/2886
摘要： A probe card for testing semiconductor wafers, and a method and system for testing wafers using the probe card are provided. The probe card is configured for use with a conventional testing apparatus, such as a wafer probe handler, in electrical communication with test circuitry. The probe card includes an interconnect substrate having contact members for establishing electrical communication with contact locations on the wafer. The probe card also includes a membrane for physically and electrically connecting the interconnect substrate to the testing apparatus, and a compressible member for cushioning the pressure exerted on the interconnect substrate by the testing apparatus. The interconnect substrate can be formed of silicon with raised contact members having penetrating projections. Alternately the contact members can be formed as indentations for testing bumped wafers. The membrane can be similar to multi layered TAB tape including metal foil conductors attached to a flexible, electrically-insulating, elastomeric tape. The probe card can be configured to contact all of the dice on the wafer at the same time, so that test signals can be electronically applied to selected dice as required.
摘要翻译：提供了用于测试半导体晶片的探针卡，以及使用探针卡测试晶片的方法和系统。探针卡被配置用于与测试电路电气通信的常规测试装置，例如晶片探测器处理器。探针卡包括具有用于与晶片上的接触位置建立电连通的接触构件的互连基板。探针卡还包括用于将互连基板物理和电连接到测试装置的膜，以及用于缓冲由测试装置施加在互连基板上的压力的可压缩构件。互连衬底可以由具有穿透突起的凸起接触构件的硅形成。或者，接触构件可以形成为用于测试凸起的晶片的凹陷。膜可以类似于多层TAB带，其包括附接到柔性，电绝缘的弹性体带的金属箔导体。探针卡可以配置为同时接触晶片上的所有骰子，以便测试信号可以根据需要以电子方式应用于选定的骰子。

47. 发明授权

US06392429B1 Temporary semiconductor package having dense array external contacts 失效
标题翻译：具有密集阵列外部触点的临时半导体封装
公开(公告)号：US06392429B1
公开(公告)日：2002-05-21
申请号：US09594748
申请日：2000-06-14
申请人： David R. Hembree , Warren M. Farnworth , Alan G. Wood , Salman Akram
发明人： David R. Hembree , Warren M. Farnworth , Alan G. Wood , Salman Akram
IPC分类号： G01R3102
CPC分类号： H01L23/49838 , G01R1/0433 , G01R1/0466 , G01R1/0483 , G01R1/0735 , G01R3/00 , G01R31/2863 , H01L21/6835 , H01L22/20 , H01L23/13 , H01L23/49816 , H01L24/80 , H01L2224/05571 , H01L2224/05573 , H01L2224/16145 , H01L2225/06562 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H05K3/0058 , H05K3/0067 , H05K3/4007 , H05K3/423 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , H01L2224/05599
摘要： A temporary package for a semiconductor die is provided. The temporary package has an outline and external contact configuration that are the same as a conventional plastic or ceramic semiconductor package. The temporary package can be used for burn-in testing of the die using standard equipment. The die can then be removed from the package and certified as a known good die. The package includes a base, an interconnect and a force applying mechanism. The package base includes external contacts formed in a dense array, such as a land grid array (LGA), a pin grid array (PGA), a bumped grid array (BGA) or a perimeter array. The package base can be formed of ceramic or plastic with internal conductive lines using a ceramic lamination process, a 3-D molding process or a Cerdip formation process.
摘要翻译：提供了一种用于半导体管芯的临时封装。临时包装具有与常规塑料或陶瓷半导体封装相同的轮廓和外部接触构造。临时包装可用于使用标准设备对模具进行老化测试。然后可以将模具从包装中取出并被认证为已知的好的模具。该包装包括底座，互连和力施加机构。封装基座包括形成在密集阵列中的外部触头，例如焊盘格栅阵列（LGA），引脚格栅阵列（PGA），凸起栅格阵列（BGA）或周边阵列。封装基底可以由具有内部导电线的陶瓷或塑料形成，使用陶瓷层压工艺，3-D成型工艺或Cerdip形成工艺。

48. 发明授权

US06358833B1 Method of fabricating a micromachined chip scale package 失效
标题翻译：制造微加工芯片级封装的方法
公开(公告)号：US06358833B1
公开(公告)日：2002-03-19
申请号：US09651601
申请日：2000-08-30
申请人： Salman Akram , David R. Hembree , Warren M. Farnworth
发明人： Salman Akram , David R. Hembree , Warren M. Farnworth
IPC分类号： H01L2144
CPC分类号： H01L23/13 , H01L24/11 , H01L24/13 , H01L2224/0231 , H01L2224/0401 , H01L2224/05147 , H01L2224/05171 , H01L2224/05647 , H01L2224/1148 , H01L2224/13099 , H01L2224/131 , H01L2224/1319 , H01L2224/13339 , H01L2224/16237 , H01L2924/0001 , H01L2924/00013 , H01L2924/01005 , H01L2924/01013 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10329 , H01L2924/14 , H01L2924/15787 , H01L2924/19041 , H01L2924/19043 , H01L2224/29099 , H01L2924/00014 , H01L2924/0665 , H01L2924/00 , H01L2924/013
摘要： A chip scale package comprised of a semiconductor die having a silicon blank laminated to its active surface. The bond pads of the die are accessed through apertures micromachined through the blank. The package may be employed with wire bonds, or solder or other conductive bumps may be placed in the blank apertures for flip-chip applications. Further, the package may be employed to reroute external connections of the die to other locations, such as a centralized ball grid array or in an edge-connect arrangement for direct or discrete die connect (DDC) to a carrier. It is preferred that the chip scale package be formed at the wafer level, as one of a multitude of packages so formed with a wafer-level blank, and that the entire wafer be burned-in and tested to identify the known good die (KGD) before the wafer laminate is separated into individual packages.
摘要翻译：芯片级封装由半导体管芯组成，半导体管芯具有层压在其有源表面上的硅片。模具的接合焊盘通过微机械加工通过坯件的孔进入。该封装可以与引线接合使用，或者可以将焊料或其它导电凸块放置在用于倒装芯片应用的空白孔中。此外，可以使用封装将管芯的外部连接重新路由到其他位置，例如集中式球栅阵列或用于直接或离散管芯连接（DDC）到载体的边缘连接装置。优选的是，芯片级封装形成在晶片级，作为如此形成的多个封装之一，其形成有晶片级坯料，并且整个晶片被烧入并测试以识别已知的良好裸片（KGD ），然后将晶片层压板分离成单个包装。

49. 发明授权

US06313651B1 Carrier and system for testing bumped semiconductor components 失效
标题翻译：用于测试碰撞半导体元件的载体和系统
公开(公告)号：US06313651B1
公开(公告)日：2001-11-06
申请号：US09322724
申请日：1999-05-28
申请人： David R. Hembree , Warren M. Farnworth , Alan G. Wood , Derek Gochnour , Salman Akram
发明人： David R. Hembree , Warren M. Farnworth , Alan G. Wood , Derek Gochnour , Salman Akram
IPC分类号： G01R3102
CPC分类号： G01R1/0483 , H01L2224/0401 , H01L2224/05552 , H01L2224/48091 , H01L2224/81385 , H01L2924/01021 , H01L2924/01087 , H01L2924/09701 , H01L2924/10155 , H01L2924/15311 , H01L2924/00014
摘要： A semiconductor carrier and system for testing bumped semiconductor components, such as dice and packages, having contact bumps are provided. The carrier includes a base, an interconnect, and a force applying mechanism. The interconnect includes patterns of contact members adapted to electrically contact the contact bumps. The interconnect can include a substrate having contact members formed as recesses, or as projections, covered with conductive layers. Alternately, the interconnect can be a multi layered tape bonded directly to a base of the carrier. In addition to providing electrical connections, the contact members perform an alignment function by self centering the contact bumps within the contact members. The carrier can also include an alignment member configured to align the components with the interconnect. The system can include the carrier, a socket, and a testing apparatus such as a burn-in board in electrical communication with test circuitry.
摘要翻译：提供了一种半导体载体和系统，用于测试具有接触凸块的凸起的半导体部件，例如芯片和封装。载体包括基底，互连和力施加机构。互连包括适于电接触接触凸块的接触构件的图案。互连可以包括具有形成为凹陷的接触构件的衬底，或者作为突出部的覆盖有导电层的衬底。或者，互连可以是直接结合到载体的基底的多层带。除了提供电连接之外，接触构件通过使接触构件内的接触凸块自对中来执行对准功能。载体还可以包括配置成将部件与互连对准的对准部件。该系统可以包括载体，插座和诸如与测试电路电连接的老化板的测试装置。

50. 发明授权

US06285203B1 Test system having alignment member for aligning semiconductor components 有权
公开(公告)号：US06285203B1
公开(公告)日：2001-09-04
申请号：US09332838
申请日：1999-06-14
申请人： Salman Akram , Warren M. Farnworth , Michael E. Hess , David R. Hembree
发明人： Salman Akram , Warren M. Farnworth , Michael E. Hess , David R. Hembree
IPC分类号： G01R102
CPC分类号： G01R1/0483 , G01R31/2886 , H01L2224/05554 , H01L2224/05571 , H01L2224/05573 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L2224/8592 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/09701 , H01L2924/10157 , H01L2924/10253 , H01L2924/15312 , H01L2924/1815 , H01L2924/00014 , H01L2924/00
摘要： A test system for testing semiconductor components includes an interconnect having contacts for making temporary electrical connections with terminal contacts on the components. The interconnect contacts can be configured to electrically engage planar terminal contacts (e.g., bond pads, test pads) or bumped terminal contacts (e.g., solder bumps, solder balls) on the components. The test system also includes an alignment member for aligning the components to the interconnect. Different embodiments of the alignment member include: a curable polymer material molded in place on the interconnect; an alignment opening formed as an etched pocket in a substrate of the interconnect; and a separate fence attached to the interconnect using an alignment fixture.

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