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    • 43. 发明授权
    • 3-layer VPN and constructing method thereof
    • 3层VPN及其构建方法
    • US07411955B2
    • 2008-08-12
    • US10336156
    • 2003-01-03
    • Bing LiWeisi Dong
    • Bing LiWeisi Dong
    • H04L12/56
    • H04L45/00H04L45/50
    • A 3-layer Virtual Private Network (VPN) is disclosed and includes P devices and PE devices in the backbone network, a plurality of sites and CE devices in subscribers' VPNs, and Hierarchy of PE (HoPE) devices, the HoPE devices serve as edge routers in the backbone network and are connected to P devices in the backbone network as well as sites and CE devices in subscribers' VPNs; the HoPE devices include understratum PEs (UPEs), zero or more middle-level PEs (MPEs) and superior PEs (SPEs) connected with each other, and all of the PEs (UPEs, MPEs, and SPEs) take different roles and deliver the function of a central PE. For the SPEs, the routing and forwarding performance should be relatively higher; while for UPEs, the performance may be lower. The architecture can enhance the expandability in hierarchical BGP/MPLS VPNs.
    • 公开了一种三层虚拟专用网(VPN),其中包括骨干网中的P设备和PE设备,用户VPN中的多个站点和CE设备以及PE(HoPE)设备层次结构,HoPE设备作为 骨干网络中的边缘路由器,并连接到骨干网中的P设备以及用户VPN中的站点和CE设备; HoPE设备包括相互连接的底层PE(UPE),零个或多个中间PE(MPE)和上级PE(SPE),所有PE(UPE,MPE和SPE)具有不同的角色,并提供 中央PE功能。 对于SPE,路由和转发性能应相对较高; 而对于UPE,性能可能会较低。 该架构可以增强分层BGP / MPLS VPN的可扩展性。
    • 48. 发明授权
    • CMOS process active waveguides on five layer substrates
    • CMOS工艺有源波导在五层基板上
    • US07218826B1
    • 2007-05-15
    • US11214704
    • 2005-08-29
    • Lawrence C. Gunn, IIIThierry J. PinguetMaxime Jean RattierBing Li
    • Lawrence C. Gunn, IIIThierry J. PinguetMaxime Jean RattierBing Li
    • G02B6/10G02B6/12
    • G02B6/12004G02B6/132
    • A standard CMOS process is used to fabricate optical, optoelectronic and electronic devices at the same time on a monolithic integrated circuit. FIG. 12 shows an active waveguide formed by a standard CMOS process on a five layer substrate. The waveguide is a silicon strip loaded waveguide with a three layer core made of a silicon strip on a silicon slab with a silicon dioxide layer between the strip and slab. The active waveguide has two doped regions in the silicon slab adjacent to and on either side of the waveguide. FIG. 12A is a table summarizing the elements of the waveguide of FIG. 12 and the CMOS transistors of FIGS. 1 and 2, which are formed from the same materials at the same time on the same silicon substrate. In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical elements such as the core of an optical waveguide or a light scatterer will damage the elements and prevent the passage of light through those sections of the elements. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide or a light scatterer, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide and a light scatterer.
    • 标准CMOS工艺用于在单片集成电路上同时制造光学,光电子和电子器件。 图。 图12示出了通过五层基板上的标准CMOS工艺形成的有源波导。 波导是带硅负载波导,其具有由硅板上的硅带制成的三层芯,其中带和板之间具有二氧化硅层。 有源波导在邻近波导的两侧的硅片中具有两个掺杂区域。 图。 图12A是总结图1的波导的元件的表格。 图12和图8的CMOS晶体管。 在相同的硅衬底上同时由相同的材料形成1和2。 在标准CMOS工艺中,金属硅化物层可以沉积在集成电路的那些选定部分上,期望具有诸如晶体管的电子部件的金属接触。 将自对准硅化物沉积到诸如光波导或光散射体的核心的光学元件中将损坏元件并防止光通过元件的那些部分。 在沉积硅化物之前,将硅化物阻挡层沉积在诸如在光波导或光散射体上的集成电路的那些部分上,这些部分将被保护以防止通过沉积硅化物而损坏。 硅化物阻挡层用作硅波导和光散射体的包层的一层。