专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明授权

US5808346A Semiconductor device structure which provides individually controllable body-terminal voltage of MOS transistors 失效
标题翻译：提供MOS晶体管的单独可控的体电极端电压的半导体器件结构
公开(公告)号：US5808346A
公开(公告)日：1998-09-15
申请号：US770422
申请日：1996-12-20
申请人： Kimio Ueda
发明人： Kimio Ueda
IPC分类号： H01L21/8238 , H01L21/84 , H01L27/088 , H01L27/092 , H01L27/12 , H01L29/10 , H01L29/786 , H01L29/41
CPC分类号： H01L29/78696 , H01L21/84 , H01L27/088 , H01L27/1203 , H01L29/1087 , H01L29/78612
摘要： An N-type well region (NW) is provided on a P-type bulk silicon substrate (PS), and a channel region (PC) is provided inside the N-type well region (NW). The channel region is formed of a semiconductor layer having a polarity opposite to that of a source region (ST) and a drain region (DT). A contact hole (CHC) is provided in a gate oxide film (GO) located below a main portion (MP) close to an end portion (EP) of a gate electrode (GT). With this construction, a semiconductor device in which a body terminal is connected to a gate terminal for fast operation can remove restriction on location for connecting the body terminal and the gate terminal to achieve size-reduction and overcome disadvantages due to restriction on supply voltage.
摘要翻译：在P型体硅衬底（PS）上设置有N型阱区（NW），在N型阱区（NW）内设置有沟道区（PC）。沟道区域由与源极区域（ST）和漏极区域（DT）的极性相反的极性的半导体层形成。在靠近栅极（GT）的端部（EP）的主要部分（MP）下方的栅极氧化膜（GO）中设置接触孔（CHC）。利用这种结构，其中主体端子连接到用于快速操作的栅极端子的半导体器件可以消除对用于连接主体端子和栅极端子的位置的限制，以实现尺寸减小并且克服由于电源电压的限制而导致的缺点。

42. 发明授权

US5572152A Logic circuit with the function of controlling discharge current on pull-down and emitter coupled logic circuit 失效
标题翻译：逻辑电路具有控制下拉和发射极耦合逻辑电路放电电流的功能
公开(公告)号：US5572152A
公开(公告)日：1996-11-05
申请号：US573604
申请日：1995-12-15
申请人： Kimio Ueda
发明人： Kimio Ueda
IPC分类号： H03K19/086 , H03K19/013 , H03K19/20
CPC分类号： H03K19/0136 , H03K19/086
摘要： A first current switch circuit 1a outputs a first logic signal and a complementary signal thereof in response to an input logic signal. A pull-up transistor Q10 has a base receiving the first logic signal. A second current switch circuit 1b outputs a second logic signal based on the complementary signal and the potential of an output terminal OUT1. A level shift circuit 1c shifts the level of the second logic signal and provides it to the base of a pull-down transistor Q11. When the potential of an input terminal IN1 changes from a low level to a high level, a capacitive load CL is discharged through transistors Q9 and Q11. When the potential of output terminal OUT1 becomes lower than that of a first reference potential terminal VBB1, the second logic signal attains a low level, thereby turning off pull-down transistor Q11.
摘要翻译：第一电流开关电路1a响应于输入逻辑信号输出第一逻辑信号及其互补信号。上拉晶体管Q10具有接收第一逻辑信号的基极。第二电流开关电路1b基于互补信号和输出端子OUT1的电位输出第二逻辑信号。电平移位电路1c使第二逻辑信号的电平移位并将其提供给下拉晶体管Q11的基极。当输入端子IN1的电位从低电平变化到高电平时，电容性负载CL通过晶体管Q9和Q11放电。当输出端子OUT1的电位变得低于第一参考电位端子VBB1的电位时，第二逻辑信号达到低电平，从而关断下拉晶体管Q11。

43. 发明授权

US5298774A Gate array system semiconductor integrated circuit device 失效
标题翻译：门阵列系统半导体集成电路器件
公开(公告)号：US5298774A
公开(公告)日：1994-03-29
申请号：US844920
申请日：1992-03-05
申请人： Kimio Ueda , Yasunobu Nakase
发明人： Kimio Ueda , Yasunobu Nakase
IPC分类号： H01L27/02 , H01L27/118 , H01L27/10
CPC分类号： H01L27/11807 , H01L27/0203
摘要： Disclosed is a semiconductor integrated circuit device of a gate array system making it possible to mount a digital circuit and a high-precision analog circuit on a common substrate. This semiconductor integrated circuit device includes a basic cell array formed by a plurality of NMOS transistors and a plurality of PMOS transistors formed in rows on a semiconductor substrate. The basic cell array includes a plurality of N well regions formed in rows on the semiconductor substrate, P well regions and well terminal regions. The P well regions or N well regions are divided into small regions of the other conductivity type.
摘要翻译：公开了一种门阵列系统的半导体集成电路器件，使得可以在公共衬底上安装数字电路和高精度模拟电路。该半导体集成电路器件包括由多个NMOS晶体管形成的基本单元阵列和在半导体衬底上以行形成的多个PMOS晶体管。基本单元阵列包括在半导体衬底上的行中形成的多个N阱区，P阱区和阱端子区。 P阱区或N阱区分为另一种导电类型的小区域。

44. 发明授权

US5072285A Semiconductor integrated circuit having region for forming complementary field effect transistors and region for forming bipolar transistors 失效
标题翻译：具有用于形成互补场效应晶体管的区域和用于形成双极晶体管的区域的半导体集成电路
公开(公告)号：US5072285A
公开(公告)日：1991-12-10
申请号：US482954
申请日：1990-02-22
申请人： Masahiro Ueda , Toshiaki Hanibuchi , Kimio Ueda
发明人： Masahiro Ueda , Toshiaki Hanibuchi , Kimio Ueda
IPC分类号： H01L21/8249 , H01L21/82 , H01L27/06 , H01L27/118 , H03K19/08
CPC分类号： H01L27/11896
摘要： A Bi-CMOS gate array comprises basic cells combining CMOS transistors and bipolar transistors. The basic cell is formed of a region for forming p-MOS transistors, a region for forming n-MOS transistors and a region for forming bipolar transistors. The region for forming p-MOS transistors comprises gates aligned spaced apart from each other in a first direction and p-type source and drain regions formed spaced apart from each other in the first direction so as to be disposed at the opposite sides of each gate and having a predetermined width. The region for forming n-MOS transistors comprises gates formed spaced apart from each other in the first direction and n-type source and drain regions formed spaced apart from each other in the first direction so as to be disposed at the opposite sides of each gate and having a predetermined width. The region for forming bipolar transistors comprises p-type source or drain region of the region for forming p-MOS transistors as a base region, and an n-type emitter region formed in the base region and a region for taking out the potential of substrate of the p-MOS transistor as a collector region. An npn bipolar transistor formed in the region for forming p-MOS transistors can be electrically isolated from the other p-MOS transistor and used by holding gates disposed at the opposite sides of the base region at a power supply potential.
摘要翻译：双CMOS门阵列包括组合CMOS晶体管和双极晶体管的基本单元。基本单元由用于形成p-MOS晶体管的区域，用于形成n-MOS晶体管的区域和用于形成双极晶体管的区域形成。用于形成p-MOS晶体管的区域包括在第一方向上彼此间隔开的栅极和在第一方向上彼此间隔开形成的p型源极和漏极区域，以便设置在每个栅极的相对侧并具有预定的宽度。用于形成n-MOS晶体管的区域包括在第一方向上彼此间隔开的栅极和在第一方向上彼此间隔开形成的n型源极和漏极区域，以便设置在每个栅极的相对侧并具有预定的宽度。用于形成双极晶体管的区域包括用于形成p-MOS晶体管作为基极区域的区域的p型源极或漏极区域，以及形成在基极区域中的n型发射极区域和用于取出衬底的电位的区域作为集电极区域的p-MOS晶体管。在用于形成p-MOS晶体管的区域中形成的npn双极晶体管可以与另一个p-MOS晶体管电隔离，并且通过将栅极设置在基极区域的相对侧处于供电电位来使用。

45. 发明授权

US4399106A Reactor for preparing uranium trioxide 失效
标题翻译：用于制备三氧化铀的反应器
公开(公告)号：US4399106A
公开(公告)日：1983-08-16
申请号：US295999
申请日：1981-08-25
申请人： Kimio Ueda
发明人： Kimio Ueda
IPC分类号： B01J8/26 , B01J8/34 , B01J8/36 , C01G43/01 , C01G56/00
CPC分类号： B01J8/26 , B01J8/34 , C01G43/01 , C01G56/004 , C01G56/005 , Y10S422/903
摘要： Nuclear fuels, such as uranium trioxide, are prepared by thermal decomposition of a nitrate in a fluidized bed reactor. The fluidized bed reactor for preparing uranium trioxide from uranyl nitrate by thermal decomposition has (a) a rectangularly shaped bed which satisfies the critical safety shape of .sup.235 U, (b) plural holes to supply an aqueous solution of uranyl nitrate into the reactor, (c) at least two reaction rooms divided by barriages, the bottoms of the barriers being capable of being lifted to control their distance from the floor and a mechanism by which uranium trioxide powder is taken out mainly by being overflowed from the top of the barriers through the reaction rooms, (d) heating means inside and outside of the fluidized-bed, and (e) a head structure which is upwardly V-shaped. Continuous operation can be attained with ease, and uranium trioxide can be made efficiently.
摘要翻译：核燃料，如三氧化铀，通过在流化床反应器中热分解硝酸盐来制备。用于通过热分解从硝酸铀酯制备三氧化铀的流化床反应器具有（a）满足235U的关键安全形状的矩形床，（b）将硝酸铀酰水溶液供应到反应器中的多个孔，（c ）至少两个反应室被分隔开，障碍物的底部能够被提升以控制其离开地板的距离以及主要通过从屏障的顶部溢出的机制，铀三氧化物粉末被引出反应室，（d）流化床内部和外部的加热装置，和（e）向上V形的头部结构。可以容易地实现连续操作，并且可以有效地制备三氧化二铀。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式