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41. 发明授权

US08692364B2 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US08692364B2
公开(公告)日：2014-04-08
申请号：US13389234
申请日：2010-08-06
申请人： Katsumi Kikuchi , Yoshiki Nakashima , Kentaro Mori , Shintaro Yamamichi
发明人： Katsumi Kikuchi , Yoshiki Nakashima , Kentaro Mori , Shintaro Yamamichi
IPC分类号： H01L23/06 , H01L23/48 , H01L23/02 , H01L23/522 , H01L21/4763 , H01L21/48
CPC分类号： H05K1/185 , H01L23/49827 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L25/105 , H01L2224/04105 , H01L2224/12105 , H01L2224/24226 , H01L2224/73267 , H01L2224/92 , H01L2225/1035 , H01L2225/1058 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/10329 , H01L2924/12044 , H01L2924/1461 , H01L2924/15311 , H01L2924/15331 , H01L2924/19041 , H01L2924/3511 , H05K1/0366 , H05K3/4682 , H05K2201/029 , H05K2201/10674 , H05K2203/063 , H05K2203/1469 , H01L2224/83 , H01L2224/82 , H01L2924/00
摘要： A semiconductor device includes an embedding layer in which one or more semiconductor element(s) is embedded and one or more interconnect layers as well as one or more insulation layers on one or both sides of the embedding layer. The embedding layer includes a woven cloth formed by reinforcement fibers. The woven cloth has an opening on its site embedding the semiconductor element. The opening is arranged so that direction of the reinforcement fibers will have a preset angle with respect to a direction of a side of or a tangent to at least a portion of the opening, the preset angle being other than a square angle or a zero angle (parallelism).
摘要翻译：一种半导体器件包括其中嵌入一个或多个半导体元件的嵌入层和一个或多个互连层以及在嵌入层的一侧或两侧上的一个或多个绝缘层。嵌入层包括由增强纤维形成的织布。编织布在其内部具有嵌入半导体元件的开口。开口被布置成使得加强纤维的方向相对于开口的至少一部分的一侧的方向或切线的方向具有预设角度，预设角度不同于方角或零角度（并行）。

42. 发明授权

US08569892B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08569892B2
公开(公告)日：2013-10-29
申请号：US13062262
申请日：2009-10-05
申请人： Kentaro Mori , Daisuke Ohshima , Shintaro Yamamichi , Hideya Murai , Katsumi Maeda , Katsumi Kikuchi , Yoshiki Nakashima
发明人： Kentaro Mori , Daisuke Ohshima , Shintaro Yamamichi , Hideya Murai , Katsumi Maeda , Katsumi Kikuchi , Yoshiki Nakashima
IPC分类号： H01L23/48 , H01L23/10
CPC分类号： H01L24/85 , H01L23/13 , H01L23/142 , H01L23/49827 , H01L23/5389 , H01L23/552 , H01L24/19 , H01L24/24 , H01L24/28 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/91 , H01L24/92 , H01L2223/54426 , H01L2223/54473 , H01L2223/6677 , H01L2224/04105 , H01L2224/2402 , H01L2224/24226 , H01L2224/24227 , H01L2224/32245 , H01L2224/45015 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/484 , H01L2224/48599 , H01L2224/73227 , H01L2224/73265 , H01L2224/73267 , H01L2224/82039 , H01L2224/82047 , H01L2224/85 , H01L2224/92 , H01L2224/92244 , H01L2224/92247 , H01L2924/00014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01073 , H01L2924/01078 , H01L2924/01079 , H01L2924/01083 , H01L2924/014 , H01L2924/078 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/1517 , H01L2924/15174 , H01L2924/15311 , H01L2924/157 , H01L2924/181 , H01L2924/18162 , H01L2924/19041 , H01L2924/3011 , H01L2924/3025 , H01L2224/83 , H01L2224/82 , H01L2924/3512 , H01L2924/00 , H01L2924/00012 , H01L2224/85399 , H01L2224/05599
摘要： A semiconductor device includes: at least one semiconductor element having electrode terminals; a metal plate supporting the semiconductor element; and a wiring board covering the semiconductor element and including a plurality of insulating layers and wiring layers alternately stacked and external connection terminals on a surface, the wiring layers being electrically connected to each other by vias. The electrode terminals and the external connection terminals are electrically connected via at least one of the wiring layers and the vias. At least one of the electrode terminals, the is wiring layers, and the vias is electrically connected to the metal plate.
摘要翻译：半导体器件包括：至少一个具有电极端子的半导体元件; 支撑半导体元件的金属板; 以及覆盖半导体元件并且在表面上交替堆叠的多个绝缘层和布线层以及外部连接端子的布线板，布线层通过通孔彼此电连接。电极端子和外部连接端子经由布线层和通孔中的至少一个电连接。至少一个电极端子，即布线层和通孔，电连接到金属板。

43. 发明申请

US20120300425A1 FUNCTIONAL ELEMENT BUILT-IN SUBSTRATE AND WIRING SUBSTRATE 有权
标题翻译：功能元件内置基板和接线基板
公开(公告)号：US20120300425A1
公开(公告)日：2012-11-29
申请号：US13574455
申请日：2011-01-07
申请人： Yoshiki Nakashima , Shintaro Yamamichi , Katsumi Kikuchi , Kentaro Mori , Hideya Murai
发明人： Yoshiki Nakashima , Shintaro Yamamichi , Katsumi Kikuchi , Kentaro Mori , Hideya Murai
IPC分类号： H05K1/18 , H05K1/11
CPC分类号： H05K1/182 , H01L23/49838 , H01L23/5389 , H01L24/19 , H01L2224/04105 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2924/12042 , H01L2924/15153 , H01L2924/18162 , H05K1/0298 , H05K1/115 , H05K1/185 , Y10T29/49126 , Y10T29/49165 , Y10T428/24322 , H01L2924/00
摘要： An object of the present invention is to propose a functional element built-in substrate which enables an electrode terminal of a functional element to be well connected to the back surface on the side opposite to the electrode terminal of the functional element, and which can be miniaturized. According to the present invention, there is provided a functional element built-in substrate including a functional element provided with an electrode terminal on one surface side of the functional element, and a wiring substrate including a laminated structure in which the functional element is embedded so that the electrode terminal of the functional element faces the front surface side of the structure, and which is formed at least in a side surface region of the functional element by laminating a plurality of wiring insulating layers each including a wiring, the functional element built-in substrate being featured in that the electrode terminal and the back surface side of the wiring substrate are electrically connected to each other through the wiring of the laminated structure, and in that, in a pair of the wiring insulating layers included in the laminated structure and that are in contact with each other, the cross-sectional shape of the wiring in each of the wiring insulating layers, which cross-sectional shape is taken along the plane perpendicular to the extension direction of the wiring in the wiring insulating layer, has a relationship that the cross-sectional area of the wiring in the back surface side wiring insulating layer is larger than the cross-sectional area of the wiring in the front surface side wiring insulating layer.
摘要翻译：本发明的目的是提出一种功能元件内置基板，其使功能元件的电极端子能够良好地连接到与功能元件的电极端子相反的一侧的背面，并且其可以是小型化。根据本发明，提供了一种功能元件内置基板，其包括在功能元件的一个表面侧上设置有电极端子的功能元件，以及包括功能元件嵌入其中的层叠结构的布线基板所述功能元件的电极端子面向所述结构的前表面侧，并且通过层叠多个布线绝缘层而形成在所述功能元件的至少侧面区域中，所述多个布线绝缘层包括布线，其特征在于，布线基板的电极端子和背面侧通过层叠结构的布线电连接，并且其中，在层叠结构中包括的一对布线绝缘层和彼此接触，每个布线绝缘中的布线的横截面形状与布线绝缘层中的配线的延伸方向垂直的平面截取的截面形状的层具有这样的关系：背面侧配线绝缘层中的布线的截面积大于表面侧配线绝缘层中的配线的截面积。

44. 发明申请

US20120153501A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120153501A1
公开(公告)日：2012-06-21
申请号：US13392714
申请日：2010-08-27
申请人： Hideya Murai , Kentaro Mori , Shintaro Yamamichi , Masahiro Komuro , Masaya Kawano
发明人： Hideya Murai , Kentaro Mori , Shintaro Yamamichi , Masahiro Komuro , Masaya Kawano
IPC分类号： H01L23/538 , H01L21/56
CPC分类号： H01L23/5389 , H01L23/14 , H01L23/49816 , H01L23/544 , H01L24/02 , H01L24/13 , H01L24/19 , H01L24/20 , H01L2223/54473 , H01L2223/5448 , H01L2223/54486 , H01L2224/02379 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/13024 , H01L2224/20 , H01L2224/211 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/92244 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12044 , H01L2924/14 , H01L2924/15153 , H01L2924/1517 , H01L2924/15174 , H01L2924/15311 , H01L2924/18162 , H05K1/185 , H05K3/4644 , H05K2201/10674 , H01L2224/24227
摘要： In a semiconductor device in which the semiconductor chip including the external terminal(s) is embedded in an insulating layer and interconnect conductor(s) is (are) formed on the insulating layer, base hole(s) is (are) formed at position(s) of the insulating layer corresponding to the external terminal(s) in a state where the semiconductor chip has shrunk after having been embedded in the insulating layer. The interconnect conductor(s) is (are) electrically connected to the external terminal(s) through the base hole(s).
摘要翻译：在绝缘层上形成包括外部端子的半导体芯片嵌入绝缘层和互连导体的半导体装置中，在位置上形成有基底孔，在半导体芯片已经被嵌入绝缘层之后已经收缩的状态下与外部端子对应的绝缘层的一个或多个。互连导体通过基座孔电连接到外部端子。

45. 发明申请

US20120133052A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120133052A1
公开(公告)日：2012-05-31
申请号：US13389234
申请日：2010-08-06
申请人： Katsumi Kikuchi , Yoshiki Nakashima , Kentaro Mori , Shintaro Yamamichi
发明人： Katsumi Kikuchi , Yoshiki Nakashima , Kentaro Mori , Shintaro Yamamichi
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H05K1/185 , H01L23/49827 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L25/105 , H01L2224/04105 , H01L2224/12105 , H01L2224/24226 , H01L2224/73267 , H01L2224/92 , H01L2225/1035 , H01L2225/1058 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01049 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/10329 , H01L2924/12044 , H01L2924/1461 , H01L2924/15311 , H01L2924/15331 , H01L2924/19041 , H01L2924/3511 , H05K1/0366 , H05K3/4682 , H05K2201/029 , H05K2201/10674 , H05K2203/063 , H05K2203/1469 , H01L2224/83 , H01L2224/82 , H01L2924/00
摘要： A semiconductor device includes an embedding layer in which one or more semiconductor element(s) is embedded and one or more interconnect layers as well as one or more insulation layers on one or both sides of the embedding layer. The embedding layer includes a woven cloth formed by reinforcement fibers. The woven cloth has an opening on its site embedding the semiconductor element. The opening is arranged so that direction of the reinforcement fibers will have a preset angle with respect to a direction of a side of or a tangent to at least a portion of the opening, the preset angle being other than a square angle or a zero angle (parallelism).
摘要翻译：一种半导体器件包括其中嵌入一个或多个半导体元件的嵌入层和一个或多个互连层以及在嵌入层的一侧或两侧上的一个或多个绝缘层。嵌入层包括由增强纤维形成的织布。编织布在其内部具有嵌入半导体元件的开口。开口被布置成使得加强纤维的方向相对于开口的至少一部分的一侧的方向或切线的方向具有预设角度，预设角度不同于方角或零角度（并行）。

46. 发明授权

US08050050B2 Wiring board, semiconductor device, and method of manufacturing the same 有权
公开(公告)号：US08050050B2
公开(公告)日：2011-11-01
申请号：US12960148
申请日：2010-12-03
申请人： Shintaro Yamamichi , Katsumi Kikuchi , Yoichiro Kurita , Koji Soejima
发明人： Shintaro Yamamichi , Katsumi Kikuchi , Yoichiro Kurita , Koji Soejima
IPC分类号： H05K1/11
CPC分类号： H01L23/49816 , H01L21/6835 , H01L23/5383 , H01L23/5386 , H01L24/81 , H01L24/97 , H01L25/0657 , H01L2221/68345 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/16235 , H01L2224/81801 , H01L2224/97 , H01L2225/06517 , H01L2225/06572 , H01L2225/06586 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01038 , H01L2924/0104 , H01L2924/01056 , H01L2924/01057 , H01L2924/01072 , H01L2924/01073 , H01L2924/01082 , H01L2924/09701 , H01L2924/10329 , H01L2924/12044 , H01L2924/14 , H01L2924/15173 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30105 , H01L2924/00 , H01L2224/05599
摘要： A semiconductor device comprising a flat wiring board, a first LSI disposed on one surface of the wiring board, a sealing resin for covering the one surface and a side face of the first semiconductor element, and a second LSI disposed on another surface of the wiring board. The wiring board has conductive wiring as a wiring layer, an insulation resin as a support layer for the wiring layer, and a conductive through-hole that passes through the wiring layer and the support layer. Connection points between lands disposed in positions in which the external peripheral edges of the semiconductor elements transverse the interior of the lands as viewed vertically from above, which lands are selected from land portions on which the external connection terminals are formed, and the wiring board formed in the same plane as the lands, are unevenly distributed toward one side of the wiring board. Connections for very small wiring are thereby made possible, and a plurality of semiconductor elements can be very densely connected.

47. 发明授权

US08004085B2 Semiconductor device and method of manufacturing semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08004085B2
公开(公告)日：2011-08-23
申请号：US12593824
申请日：2008-02-13
申请人： Shintaro Yamamichi , Katsumi Kikuchi , Jun Sakai , Hikaru Kouta
发明人： Shintaro Yamamichi , Katsumi Kikuchi , Jun Sakai , Hikaru Kouta
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L27/10 , H01L29/73 , H01L29/74
CPC分类号： H01L23/5283 , H01L23/3171 , H01L23/5286 , H01L24/14 , H01L2224/05001 , H01L2224/05009 , H01L2224/05022 , H01L2224/05568 , H01L2224/0557 , H01L2224/05572 , H01L2224/056 , H01L2224/13022 , H01L2224/13111 , H01L2924/00013 , H01L2924/00014 , H01L2924/01029 , H01L2924/14 , H01L2924/19041 , H01L2924/01047 , H01L2224/13099 , H01L2924/00 , H01L2224/05099
摘要： A semiconductor device has an element interconnection 2, a top-layer element interconnection 4, a super-connect interconnection 10 and a bump 7. The element interconnection 2 is provided on a semiconductor substrate 1 through a plurality of insulating layers 50. The top-layer element interconnection 4 is formed above the element interconnection 2 by using a substantially equivalent process equipment. The super-connect interconnection 10 is provided on the top-layer element interconnection 4 through a super-connect insulating layer 9 having a thickness five or more times larger than that of the insulating layer 5, and has a thickness three or more times larger than that of each the element interconnection 2 and the top-layer element interconnection 4. The bump 7 is formed on the super-connect interconnection 10. The top-layer element interconnection 4 has a signal pad 4s, a power source pad 4v and a ground pad 4g. An area of the signal pad 4s is smaller than each area of the power source pad 4v and the ground pad 4g.
摘要翻译：半导体器件具有元件互连2，顶层元件互连4，超连接互连10和凸块7.元件互连2通过多个绝缘层50设置在半导体衬底1上。层元件互连4通过使用基本相同的处理设备形成在元件互连2上方。超连接互连10通过具有比绝缘层5的厚度大五倍以上的厚度的超连接绝缘层9设置在顶层元件布线4上，并且具有比绝缘层5的厚度大三倍以上的厚度元件互连2和顶层元件互连4中的每一个。凸块7形成在超连接互连10上。顶层元件互连4具有信号焊盘4s，电源焊盘4v和接地垫4g。信号焊盘4s的面积比电源焊盘4v和接地焊盘4g的面积小。

48. 发明申请

US20110155433A1 WIRING BOARD CAPABLE OF CONTAINING FUNCTIONAL ELEMENT AND METHOD FOR MANUFACTURING SAME 失效
标题翻译：包含功能元件的接线板及其制造方法
公开(公告)号：US20110155433A1
公开(公告)日：2011-06-30
申请号：US13060990
申请日：2009-08-25
申请人： Takuo Funaya , Shintaro Yamamichi , Daisuke Ohshima , Yoshiki Nakashima
发明人： Takuo Funaya , Shintaro Yamamichi , Daisuke Ohshima , Yoshiki Nakashima
IPC分类号： H05K1/00 , H01K3/10
CPC分类号： H05K1/115 , H01L23/145 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L2224/12105 , H01L2224/16225 , H01L2224/24051 , H01L2224/24226 , H01L2224/32225 , H01L2224/73204 , H01L2224/73267 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01019 , H01L2924/0102 , H01L2924/01023 , H01L2924/01024 , H01L2924/01025 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01038 , H01L2924/01046 , H01L2924/01047 , H01L2924/01056 , H01L2924/01073 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/09701 , H01L2924/10329 , H01L2924/3511 , H05K1/0366 , H05K1/185 , H05K3/4069 , H05K3/421 , H05K3/424 , H05K2201/0195 , H05K2201/0209 , H05K2201/09563 , H05K2201/09854 , H05K2201/2072 , Y10T29/49165 , H01L2924/00
摘要： A wiring board is configured by stacking one or more conductor wiring layers and one or more insulating resin layers and comprising one or more metal vias configured to penetrate the insulating resin layer, wherein the boundary surface between the metal via and the insulating resin layer has a concavo-convex boundary cross-section structure in which the metal via and the insulating resin layer are engaged with each other.
摘要翻译：布线板通过层叠一个或多个导体布线层和一个或多个绝缘树脂层而构成，并且包括被配置为穿透绝缘树脂层的一个或多个金属通孔，其中金属孔和绝缘树脂层之间的边界面具有金属通孔和绝缘树脂层彼此接合的凹凸边界横截面结构。

49. 发明申请

US20100117228A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20100117228A1
公开(公告)日：2010-05-13
申请号：US12593824
申请日：2008-02-13
申请人： Shintaro Yamamichi , Katsumi Kikuchi , Jun Sakai , Hikaru Kouta
发明人： Shintaro Yamamichi , Katsumi Kikuchi , Jun Sakai , Hikaru Kouta
IPC分类号： H01L23/52 , H01L23/48
CPC分类号： H01L23/5283 , H01L23/3171 , H01L23/5286 , H01L24/14 , H01L2224/05001 , H01L2224/05009 , H01L2224/05022 , H01L2224/05568 , H01L2224/0557 , H01L2224/05572 , H01L2224/056 , H01L2224/13022 , H01L2224/13111 , H01L2924/00013 , H01L2924/00014 , H01L2924/01029 , H01L2924/14 , H01L2924/19041 , H01L2924/01047 , H01L2224/13099 , H01L2924/00 , H01L2224/05099
摘要： A semiconductor device has an element interconnection 2, a top-layer element interconnection 4, a super-connect interconnection 10 and a bump 7. The element interconnection 2 is provided on a semiconductor substrate 1 through a plurality of insulating layers 50. The top-layer element interconnection 4 is formed above the element interconnection 2 by using a substantially equivalent process equipment. The super-connect interconnection 10 is provided on the top-layer element interconnection 4 through a super-connect insulating layer 9 having a thickness five or more times larger than that of the insulating layer 5, and has a thickness three or more times larger than that of each the element interconnection 2 and the top-layer element interconnection 4. The bump 7 is formed on the super-connect interconnection 10. The top-layer element interconnection 4 has a signal pad 4s, a power source pad 4v and a ground pad 4g. An area of the signal pad 4s is smaller than each area of the power source pad 4v and the ground pad 4g.
摘要翻译：半导体器件具有元件互连2，顶层元件互连4，超连接互连10和凸块7.元件互连2通过多个绝缘层50设置在半导体衬底1上。层元件互连4通过使用基本相同的处理设备形成在元件互连2上方。超连接互连10通过具有比绝缘层5的厚度大五倍以上的厚度的超连接绝缘层9设置在顶层元件布线4上，并且具有比绝缘层5的厚度大三倍以上的厚度元件互连2和顶层元件互连4中的每一个。凸块7形成在超连接互连10上。顶层元件互连4具有信号焊盘4s，电源焊盘4v和接地垫4g。信号焊盘4s的面积比电源焊盘4v和接地焊盘4g的面积小。

50. 发明申请

US20100044845A1 CIRCUIT SUBSTRATE, AN ELECTRONIC DEVICE ARRANGEMENT AND A MANUFACTURING PROCESS FOR THE CIRCUIT SUBSTRATE 审中-公开
标题翻译：电路基板，电子设备布置和电路基板的制造工艺
公开(公告)号：US20100044845A1
公开(公告)日：2010-02-25
申请号：US12298737
申请日：2007-04-27
申请人： Takuo Funaya , Shintaro Yamamichi
发明人： Takuo Funaya , Shintaro Yamamichi
IPC分类号： H01L23/52 , H01L23/48 , H01L21/50 , H01L21/768
CPC分类号： H05K1/185 , H01L21/6835 , H01L23/49827 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/50 , H01L2221/68345 , H01L2224/04105 , H01L2224/2402 , H01L2224/24051 , H01L2224/24225 , H01L2224/24226 , H01L2224/32225 , H01L2224/73267 , H01L2224/76155 , H01L2224/82102 , H01L2224/92244 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06572 , H01L2225/1035 , H01L2225/1058 , H01L2225/107 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/09701 , H01L2924/10329 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/30107 , H01L2924/3511 , H05K3/20 , H05K3/4602 , H05K3/4614 , H05K3/4652 , H05K2201/0376 , H05K2201/10378 , H05K2201/10674 , H05K2201/10969 , H05K2203/061 , H01L2924/00
摘要： [Problem to be Solved] There are provided a circuit substrate, an electronic device arrangement and a manufacturing process for the circuit substrate which enable to directly implement the surface mounting and so on of electronic components on the conductive wiring without forming solder resist, and also which enable to enhance high speed transmission characteristics and to enlarge wiring rule for the electrode terminal of the function element to be contained therein, and to implement with excellent workability and reliability when connecting the electronic device.[Solution] A circuit substrate comprising a function element 1 with an electrode terminal 5 a base member containing the function element 1 therein and having at least one layer of a conductive wiring formed on its front side face and rear side face respectively, and a via 6 connecting the electrode terminal 5 with the conductive wiring 3 formed on the base member, wherein the conductive wiring formed on either one of the front side face and the rear side face of the base member is arranged such that a surface exposed outside from the base member is in the same plane with or inside a surface of the base member on which the conductive wiring is formed.
摘要翻译： [待解决的问题]提供了一种用于电路基板的电路基板，电子器件布置和制造工艺，其能够直接实现导电布线上的电子部件的表面安装等而不形成阻焊剂，并且还能够提高高速传输特性，并且扩大要包含在其中的功能元件的电极端子的布线规则，并且在连接电子设备时实现优异的可加工性和可靠性。 [解决方案]一种电路基板，包括具有电极端子5的功能元件1，分别在其前侧面和后侧面上形成有至少一层导电布线的基座部件，其中包括功能元件1，以及通孔 6，其将电极端子5与形成在基底构件上的导电布线3连接，其中形成在基底构件的前侧面和后侧面中的任一个上的导电布线布置成使得从底部暴露出的表面构件与形成有导电布线的基底构件的表面位于同一平面内。

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