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41. 发明授权

US06770492B2 Ferroelectric memory device 失效
标题翻译：铁电存储器件
公开(公告)号：US06770492B2
公开(公告)日：2004-08-03
申请号：US10300839
申请日：2002-11-21
申请人： Hiromichi Waki , Keiichi Yoshizumi , Mitsuhiro Mori
发明人： Hiromichi Waki , Keiichi Yoshizumi , Mitsuhiro Mori
IPC分类号： H01L2100
CPC分类号： H01L27/11502 , H01L27/1085 , H01L27/10894 , H01L27/11507 , H01L28/55
摘要： This invention provides a technique for preventing film quality of a capacitive insulating film made of a ferroelectric film of a FeRAM memory cell from being degraded and for improving the characteristics of the FeRAM memory cell. A shielding film having a higher lead content than that of a capacitive insulating film is formed under a lower electrode of a capacitor in a FeRAM memory cell, and another shielding film having a higher lead content than that of the capacitive insulating film is formed on an upper electrode. PZT films to be used as barrier layers are formed in the interlayer insulating films the FeRAM memory cell. As a result, it is possible to prevent H2 or H2O from entering an upper portion or a lower portion of the capacitor, and lead diffused from the capacitive insulating film 11a can be compensated by lead included in the shielding films, and it is possible to prevent characteristics of the capacitive insulating film 11a from being degraded.
摘要翻译：本发明提供一种用于防止由FeRAM存储单元的铁电体膜构成的电容绝缘膜的膜质量降低的技术，并且用于改善FeRAM存储单元的特性。一种屏蔽膜，其铅含量高于电容绝缘膜形成在FeRAM存储单元中的电容器的下电极下方，并且在上电极上形成具有比电容绝缘膜高的铅含量的另一屏蔽膜。用作阻挡层的PZT膜在FeRAM存储单元的层间绝缘膜中形成。结果，可以防止H 2或H 2 O进入电容器的上部或下部，并且可以通过包含在屏蔽膜中的引线来补偿从电容绝缘膜11a扩散的引线，并且可以防止电容绝缘膜11a的特性劣化。

42. 发明授权

US06579754B2 Semiconductor memory device having ferroelectric film and manufacturing method thereof 失效
标题翻译：具有铁电体膜的半导体存储器件及其制造方法
公开(公告)号：US06579754B2
公开(公告)日：2003-06-17
申请号：US09850224
申请日：2001-05-08
申请人： Kazufumi Suenaga , Kiyoshi Ogata , Kazuhiko Horikoshi , Jun Tanaka , Hisayuki Kato , Keiichi Yoshizumi , Hisahiko Abe
发明人： Kazufumi Suenaga , Kiyoshi Ogata , Kazuhiko Horikoshi , Jun Tanaka , Hisayuki Kato , Keiichi Yoshizumi , Hisahiko Abe
IPC分类号： H01L218242
CPC分类号： H01L28/55 , G11C11/22 , H01L21/31691
摘要： The present invention is a high quality semiconductor memory device using a ferroelectric thin film capacitor as a memory capacitor at a high manufacturing yield, the ferroelectric thin film of the capacitor is specified such that the relative standard deviation of a crystal grain sizes is 13% or less, to thereby ensure a high remanent polarization value and a small film fatigue (large rewritable number).
摘要翻译：本发明是以制造成品率高的铁电薄膜电容器作为存储电容器的高质量的半导体存储器件，规定了电容器的铁电薄膜，晶体尺寸的相对标准偏差为13％，从而确保高的剩余极化值和小的薄膜疲劳（大的可重写数量）。

43. 发明授权

US06445025B2 Semiconductor memory device and manufacturing method thereof 失效
公开(公告)号：US06445025B2
公开(公告)日：2002-09-03
申请号：US09848420
申请日：2001-05-04
申请人： Kazufumi Suenaga , Kiyoshi Ogata , Kazuhiko Horikoshi , Jun Tanaka , Hisayuki Kato , Keiichi Yoshizumi , Hisahiko Abe
发明人： Kazufumi Suenaga , Kiyoshi Ogata , Kazuhiko Horikoshi , Jun Tanaka , Hisayuki Kato , Keiichi Yoshizumi , Hisahiko Abe
IPC分类号： H01L2976
CPC分类号： H01L28/55 , G11C11/22 , H01L21/31691
摘要： The present invention is a high quality semiconductor memory device using a ferroelectric thin film capacitor as a memory capacitor at a high manufacturing yield, the ferroelectric thin film of the capacitor is specified such that the relative standard deviation of crystal grain sizes is 13% or less, to thereby ensure a high remanent polarization value and a small film fatigue (large rewritable number).

44. 发明授权

US06316798B1 Ferroelectric memory device and method for manufacturing the same 失效
标题翻译：铁电存储器件及其制造方法
公开(公告)号：US06316798B1
公开(公告)日：2001-11-13
申请号：US09331670
申请日：1999-06-23
申请人： Kiyoshi Ogata , Kazuhiko Horikoshi , Kazufumi Suenaga , Hisayuki Kato , Keiichi Yoshizumi , Masahito Yamazaki
发明人： Kiyoshi Ogata , Kazuhiko Horikoshi , Kazufumi Suenaga , Hisayuki Kato , Keiichi Yoshizumi , Masahito Yamazaki
IPC分类号： H01L2976
CPC分类号： H01L28/57 , H01L27/1203
摘要： A long life ferroelectric memory device using a thin ferroelectric film capacitor as a memory capacitor is obtained by disposing one or a plurality of degradation preventive layers on an upper protection electrode and an upper electrode 8 and a degradation preventive layer at the boundary of ferroelectric layer 7 /electrodes 6, 8, or providing a step of decreasing a modified layer at the boundary of ferroelectric layer 7/upper electrode 8. This provides a thin ferroelectric film capacitor which is subjected to less fatigue and imprinting and which has less degradation of the ferroelectric characteristic, thereby to attain a long life ferroelectric memory device.
摘要翻译：使用薄铁电薄膜电容器作为记忆电容器的长寿命铁电存储器件通过在铁氧体层7的边界上的上保护电极和上电极8以及劣化防止层上设置一个或多个降解防止层来获得 /电极6,8，或者提供在铁电层7 /上电极8的边界处减小改性层的步骤。这提供了一种薄铁电薄膜电容器，其经受较少的疲劳和压印，并且铁电体的劣化较少特性，从而获得长寿命的铁电存储器件。

45. 发明授权

US5780328A Process for producing semiconductor integrated circuit 失效
标题翻译：半导体集成电路制造工艺
公开(公告)号：US5780328A
公开(公告)日：1998-07-14
申请号：US835197
申请日：1997-04-07
申请人： Kazushi Fukuda , Yasuko Yoshida , Yutaka Hoshino , Naotaka Hashimoto , Kyoichiro Asayama , Yuuki Koide , Keiichi Yoshizumi , Eri Okamoto , Satoru Haga , Shuji Ikeda
发明人： Kazushi Fukuda , Yasuko Yoshida , Yutaka Hoshino , Naotaka Hashimoto , Kyoichiro Asayama , Yuuki Koide , Keiichi Yoshizumi , Eri Okamoto , Satoru Haga , Shuji Ikeda
IPC分类号： H01L27/088 , H01L21/8234 , H01L21/8238 , H01L21/8239 , H01L21/8244 , H01L27/11 , H01L21/336
CPC分类号： H01L21/823814 , H01L21/823871 , H01L27/1052 , H01L27/11 , H01L27/1104
摘要： When the source and drain regions (an n.sup.- type semiconductor region and an n.sup.+ type semiconductor region) of a complementary MISFET and a p-type semiconductor region for use as a punch-through stopper are formed in a p-type well in a substrate having a p- and an n-type well, p-type impurities for the punch-through stopper are suppressed from being supplied to the feeding portion (an n.sup.+ type semiconductor region) of the n-type well.
摘要翻译：当在衬底中的p型阱中形成用作穿通阻挡层的互补MISFET和p型半导体区域的源区和漏区（n型半导体区和n +型半导体区）具有p型和n型阱时，抑制了穿通止动件的p型杂质被供给到n型阱的馈电部（n +型半导体区）。

46. 发明授权

US5328864A Method of doping gate electrodes discretely with either P-type or N-type impurities to form discrete semiconductor regions 失效
标题翻译：使用P型或N型杂质离子地掺杂栅电极以形成离散半导体区域的方法
公开(公告)号：US5328864A
公开(公告)日：1994-07-12
申请号：US699024
申请日：1991-05-13
申请人： Keiichi Yoshizumi , Satoshi Kudo
发明人： Keiichi Yoshizumi , Satoshi Kudo
IPC分类号： H01L21/768 , H01L21/28 , H01L21/8238 , H01L21/336
CPC分类号： H01L21/28026 , H01L21/823842 , Y10S148/106
摘要： The present invention relates to a method of manufacturing a semiconductor device. In a semiconductor substrate formed with a first semiconductor region of P-type and a second semiconductor region of N-type and an insulating film formed between and extending into the first and the second semiconductor regions, gate electrodes of a laminate of a polysilicon layer and a silicide layer are formed on the insulating film covering the first and the second semiconductor regions. A gate electrode situated on the first semiconductor region has an end portion facing and spaced from an end portion of a gate electrode situated on the second semiconductor region. A masking layer is formed on the second semiconductor region with an edge of the masking layer falling between the two gate electrodes where the two end portions face each other. The first semiconductor region is doped with an impurity of N-type, thereby forming a third semiconductor region in the first semiconductor region. The masking layer is removed from the second semiconductor region and a masking layer is formed on the first semiconductor region with an edge of the masking layer falling between the two gate electrodes where the two end portions face each other. The second semiconductor region is doped with an impurity of P-type, thereby forming a fourth semiconductor region in the second semiconductor region. By providing a masking layer to fall between the end portions of the gate electrodes, the gate electrodes are discretely doped to form discrete semiconductor regions.
摘要翻译：本发明涉及半导体器件的制造方法。在形成有P型的第一半导体区域和形成在第一和第二半导体区域之间并延伸到第一和第二半导体区域中的N型的第二半导体区域和绝缘膜的半导体衬底中，多晶硅层和在覆盖第一和第二半导体区域的绝缘膜上形成硅化物层。位于第一半导体区域上的栅电极具有面对并位于位于第二半导体区域上的栅电极的端部的端部。掩模层形成在第二半导体区上，其中掩模层的边缘落在两个端部彼此面对的两个栅电极之间。第一半导体区域掺杂有N型杂质，从而在第一半导体区域中形成第三半导体区域。从第二半导体区域去除掩模层，并且在第一半导体区域上形成掩模层，其中掩模层的边缘落在两个端部彼此面对的两个栅电极之间。第二半导体区域掺杂有P型杂质，从而在第二半导体区域中形成第四半导体区域。通过提供掩模层落在栅电极的端部之间，栅电极被离散地掺杂以形成分立的半导体区域。

47. 发明授权

US4776699A Optical measuring device 失效
标题翻译：光学测量装置
公开(公告)号：US4776699A
公开(公告)日：1988-10-11
申请号：US881283
申请日：1986-07-02
申请人： Keiichi Yoshizumi
发明人： Keiichi Yoshizumi
IPC分类号： G01B9/02 , G01B11/24 , G01B11/245
CPC分类号： G01B9/02007 , G01B11/24 , G01B9/02003 , G01B9/02045 , G01B9/02063 , G01B9/02068 , G01B2290/70
摘要： An optical measuring device adapted to irradiate a measuring beam on the surface of an object to be measured which is being moved relative to the measuring beam, and detect the Doppler shift of the reflected rays of the measuring beam so as to measure the surface configuration and the sizes of the object. The incident rays of the measuring beam are condensed on the surface of the object by an objective lens such that the rays reflected from the object follows the same optical path as that of the incident ray, a part of the rays reflected by the surface of the object is branched off and received by a first photodetector means including a quarter-sectioned photodetector so that the deviation of the optical path of the reflected rays from the optical path of the incident rays is detected when the inclination of the surface of the object changes, and the optical path of the incident rays is moved in the direction normal to the optical axis of the objective lens in correspondence with a signal output from the first photodetector means and indicative of the deviation, so as to avoid changing the lengths of the optical paths of the reflected rays and the incident rays.
摘要翻译：一种光学测量装置，其适于将被测量物体的表面上的测量光束照射在相对于测量光束移动的表面上，并且检测测量光束的反射光线的多普勒频移，以测量表面形状，对象的大小。测量光束的入射光线通过物镜在物体的表面上被冷凝，使得从物体反射的光线与入射光线相同的光路，与由入射光线的表面反射的一部分光线物体由包括四分之一部分的光电检测器的第一光电检测器分支和接收，使得当物体的表面的倾斜改变时，检测来自入射光线的光路的反射光线的光路的偏差，并且入射光线的光路相对于从第一光检测器装置输出的信号并且指示偏差沿垂直于物镜的光轴的方向移动，以避免改变光路的长度的反射光线和入射光线。

48. 发明授权

US08006402B2 Shape measuring apparatus and shape measuring method 有权
标题翻译：形状测量仪和形状测量方法
公开(公告)号：US08006402B2
公开(公告)日：2011-08-30
申请号：US12476518
申请日：2009-06-02
申请人： Keiichi Yoshizumi , Masateru Doi , Takayuki Kurata
发明人： Keiichi Yoshizumi , Masateru Doi , Takayuki Kurata
IPC分类号： G01B11/24 , G01B5/20
CPC分类号： G01B5/008 , G01B21/045
摘要： A moving vector calculation unit calculates a moving vector M representing a quantity and a direction of movement of a probe on basis of a stylus displacement vector, a stylus displacement vector D, and a direction change angle θ of the stylus displacement vector D that is caused by a frictional force between a stylus 32 and the measuring surface 5a during scanning of the measuring surface 5a by the stylus 32. The stylus displacement vector D is a vector including a quantity and a direction of position displacement of the stylus 32 relative to the probe 5. Movement of an XY-stage 7 is controlled so that the probe 6 moves in accordance with the moving vector M.
摘要翻译：移动矢量计算单元基于触针位移矢量，触针位移矢量D和方向改变角度来计算代表探测器的数量和移动方向的移动矢量M; 在触针32扫描测量表面5a期间由触针32和测量表面5a之间的摩擦力引起的触针位移矢量D.触针位移矢量D是包括量和位置方向的矢量触针32相对于探针5的位移。控制XY平台7的移动，使得探针6根据移动矢量M移动。

49. 发明授权

US07393737B2 Semiconductor device and a method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07393737B2
公开(公告)日：2008-07-01
申请号：US11500381
申请日：2006-08-08
申请人： Keiichi Yoshizumi , Kazuhisa Higuchi , Takayuki Nakaji , Masami Koketsu , Hideki Yasuoka
发明人： Keiichi Yoshizumi , Kazuhisa Higuchi , Takayuki Nakaji , Masami Koketsu , Hideki Yasuoka
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/82
CPC分类号： H01L27/0629 , H01L21/823462 , H01L21/823857 , H01L28/20 , H01L28/40
摘要： A semiconductor device which, in spite of the existence of a dummy active region, eliminates the need for a larger chip area and improves the surface flatness of the semiconductor substrate. In the process of manufacturing it, a thick gate insulating film for a high voltage MISFET is formed over an n-type buried layer as an active region and a resistance element IR of an internal circuit is formed over the gate insulating film. Since the thick gate insulating film lies between the n-type buried layer and the resistance element IR, the coupling capacitance produced between the substrate (n-type buried layer) and the resistance element IR is reduced.
摘要翻译：尽管存在虚拟有源区，半导体器件不需要更大的芯片面积并且提高半导体衬底的表面平坦度。在其制造过程中，在n型掩埋层上形成用于高电压MISFET的厚栅极绝缘膜作为有源区，并且在栅极绝缘膜上形成内部电路的电阻元件IR。由于厚栅极绝缘膜位于n型掩埋层和电阻元件IR之间，所以在衬底（n型掩埋层）和电阻元件IR之间产生的耦合电容减小。

50. 发明申请

US20050104098A1 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20050104098A1
公开(公告)日：2005-05-19
申请号：US10986896
申请日：2004-11-15
申请人： Hideki Yasuoka , Keiichi Yoshizumi , Masami Koketsu
发明人： Hideki Yasuoka , Keiichi Yoshizumi , Masami Koketsu
IPC分类号： H01L21/76 , H01L21/336 , H01L21/762 , H01L21/8234 , H01L21/8238 , H01L27/04 , H01L27/08 , H01L27/092 , H01L29/45 , H01L29/78 , H01L27/01 , H01L29/94 , H01L31/0392
CPC分类号： H01L29/66659 , H01L21/76229 , H01L21/823412 , H01L21/823418 , H01L21/823481 , H01L29/0653 , H01L29/456 , H01L29/7835
摘要： With the objective of suppressing or preventing a kink effect in the operation of a semiconductor device having a high breakdown voltage field effect transistor, n+ type semiconductor regions, each having a conduction type opposite to p+ type semiconductor regions for a source and drain of a high breakdown voltage pMIS, are disposed in a boundary region between each of trench type isolation portions at both ends, in a gate width direction, of a channel region of the high breakdown voltage pMIS and a semiconductor substrate at positions aced away from p− type semiconductor regions, each having a field relaxing function, of the high breakdown voltage pMIS, so as not to contact the p− type semiconductor regions (on the drain sides in particular). The n+ type semiconductor regions extend to positions deeper than the trench type isolation portions.
摘要翻译：为了抑制或防止具有高击穿电压场效应晶体管的半导体器件的操作中的扭结效应，n + +型半导体区域具有与p < 用于高击穿电压pMIS的源极和漏极的+ 型半导体区域设置在高频沟道区域的栅极宽度方向的两端的沟槽型隔离部分之间的边界区域中击穿电压pMIS和半导体衬底在远离p型 - 半导体区域的位置处，每个具有高的击穿电压pMIS的场弛豫功能，以便不接触p型 - 型半导体区域（特别是在漏极侧）。 n + +型半导体区域延伸到比沟槽型隔离部分更深的位置。

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