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41. 发明授权

US6063665A Method for silicon surface control for shallow junction formation 失效
标题翻译：浅层形成的硅表面控制方法
公开(公告)号：US6063665A
公开(公告)日：2000-05-16
申请号：US986463
申请日：1997-12-08
申请人： Nicholas H. Tripsas , David K. Foote
发明人： Nicholas H. Tripsas , David K. Foote
IPC分类号： H01L21/265 , H01L21/336
CPC分类号： H01L29/6659 , H01L21/2652
摘要： A system and method for providing a small device formed on a semiconductor is disclosed. The method and system include controlling the surface by providing a very thin oxide layer and providing a shallow implant through the very thin oxide layer.
摘要翻译：公开了一种用于提供形成在半导体上的小型器件的系统和方法。该方法和系统包括通过提供非常薄的氧化物层并通过非常薄的氧化物层提供浅的植入来控制表面。

42. 发明授权

US07561465B2 Methods and systems for recovering data in a nonvolatile memory array 有权
标题翻译：用于在非易失性存储器阵列中恢复数据的方法和系统
公开(公告)号：US07561465B2
公开(公告)日：2009-07-14
申请号：US11724774
申请日：2007-03-16
申请人： Bryan William Hancock , Nicholas H. Tripsas , Richard C. Blish, II
发明人： Bryan William Hancock , Nicholas H. Tripsas , Richard C. Blish, II
IPC分类号： G11C16/06
CPC分类号： G11C16/3404 , G11C11/5671 , G11C16/3418 , G11C16/3422 , G11C16/3431 , G11C2029/0411
摘要： One embodiment of the invention relates to a method for refreshing a nonvolatile memory array. In the method, a threshold voltage of a multi-bit memory cell is analyzed to determine if it has drifted outside of a number of allowable voltage windows, wherein each allowable voltage windows corresponds to a different multi-bit value. If the threshold voltage of the cell has drifted outside of the number of allowable voltage states, then the cell is recovered by adjusting at least one voltage boundary of at least one of the number of allowable voltage states.
摘要翻译：本发明的一个实施例涉及一种用于刷新非易失性存储器阵列的方法。在该方法中，分析多位存储单元的阈值电压以确定其是否漂移在许多允许电压窗口之外，其中每个可允许电压窗对应于不同的多位值。如果电池的阈值电压漂移在容许电压状态数之外，则通过调节至少一个容许电压状态数量的至少一个电压边界来恢复电池。

43. 发明授权

US07232765B1 Utilization of a Ta-containing cap over copper to facilitate concurrent formation of copper vias and memory element structures 有权
标题翻译：在铜上利用含Ta的盖以促进铜通孔和记忆元件结构的同时形成
公开(公告)号：US07232765B1
公开(公告)日：2007-06-19
申请号：US10988239
申请日：2004-11-12
申请人： Steven C. Avanzino , Nicholas H. Tripsas , Jeffrey A. Shields , Fei Wang , Richard P. Kingsborough , William Leonard , Suzette K. Pangrle
发明人： Steven C. Avanzino , Nicholas H. Tripsas , Jeffrey A. Shields , Fei Wang , Richard P. Kingsborough , William Leonard , Suzette K. Pangrle
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/76849 , H01L21/7685 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L51/0021
摘要： Disclosed are methods for facilitating concurrent formation of copper vias and memory element structures. The methods involve forming vias over metal lines and forming copper plugs, wherein the copper plugs comprise memory element film forming copper plugs (memE copper plugs) and non-memory element forming copper plugs (non-memE copper plugs), forming a tantalum-containing cap over an upper surface of non-memE copper plugs, and depositing memory element films. The tantalum-containing cap prevents the formation of the memory element films in the non-memE copper plugs. The subject invention advantageously facilitates cost-effective manufacturing of semiconductor devices.
摘要翻译：公开了促进铜通孔和记忆元件结构的同时形成的方法。所述方法包括在金属线上形成通孔并形成铜塞，其中铜塞包括记忆元件膜形成铜塞（memE铜塞）和形成铜塞（非memE铜塞）的非存储元件，形成含钽覆盖非memE铜插头的上表面，并沉积存储元件膜。含钽盖防止在非memE铜插头中形成记忆元件膜。本发明有利地有助于半导体器件的成本有效的制造。

44. 发明授权

US06870183B2 Stacked organic memory devices and methods of operating and fabricating 有权
标题翻译：堆叠有机存储器件及其操作和制造方法
公开(公告)号：US06870183B2
公开(公告)日：2005-03-22
申请号：US10287612
申请日：2002-11-04
申请人： Nicholas H. Tripsas , Uzodinma Okoroanyanwu , Suzette K. Pangrle , Michael A. VanBuskirk
发明人： Nicholas H. Tripsas , Uzodinma Okoroanyanwu , Suzette K. Pangrle , Michael A. VanBuskirk
IPC分类号： G11C11/56 , G11C13/02 , H01L27/28 , H01L51/00 , H01L51/30 , H01L51/20 , H01L51/40
CPC分类号： G11C13/0014 , B82Y10/00 , G11C11/5664 , G11C13/0016 , H01L27/28 , H01L51/0035 , H01L51/0036 , H01L51/0038 , H01L51/0041 , H01L51/0077 , H01L51/0078
摘要： The present invention provides a multi-layer organic memory device that can operate as a non-volatile memory device having a plurality of stacked and/or parallel memory structures constructed therein. A multi-cell and multi-layer organic memory component can be formed with two or more electrodes having a selectively conductive media between the electrodes forming individual cells, while utilizing a partitioning component to enable stacking of additional memory cells on top of or in association with previously formed cells. Memory stacks can be formed by adding additional layers—respective layers separated by additional partitioning components, wherein multiple stacks can be formed in parallel to provide a high-density memory device.
摘要翻译：本发明提供一种多层有机存储器件，其可以作为其中构造有多个堆叠和/或并行存储器结构的非易失性存储器件来操作。可以在两个或多个电极之间形成多单元和多层有机存储器组件，所述两个或更多个电极在形成各个单元的电极之间具有选择性导电介质，同时利用分隔组件使得能够堆叠额外的存储器单元，以前形成的细胞。可以通过添加额外的层 - 通过附加分隔部件分开的相应层来形成存储器堆叠，其中可以并行形成多个堆叠以提供高密度存储器件。

45. 发明授权

US06852586B1 Self assembly of conducting polymer for formation of polymer memory cell 有权
标题翻译：用于形成聚合物记忆体的导电聚合物的自组装
公开(公告)号：US06852586B1
公开(公告)日：2005-02-08
申请号：US10677042
申请日：2003-10-01
申请人： Matthew S. Buynoski , Suzette K. Pangrle , Uzodinma Okoroanyanwu , Nicholas H. Tripsas
发明人： Matthew S. Buynoski , Suzette K. Pangrle , Uzodinma Okoroanyanwu , Nicholas H. Tripsas
IPC分类号： G11C13/02 , H01L27/28 , H01L51/40 , H01L21/8234
CPC分类号： G11C13/0069 , B82Y10/00 , G11C13/0009 , G11C13/0014 , G11C13/0016 , G11C2013/009 , G11C2213/56 , G11C2213/71 , H01L27/28 , H01L51/0012
摘要： The present invention provides a selectively conductive organic semiconductor (e.g., polymer) device that can be utilized as a memory cell. A polymer solution including a conducting polymer self assembles relative to a conductive electrode. The process affords self-assembly such that a shortest conductive path can be achieved. The method includes depositing a concentrated solution of conducting polymer on a conductive surface, applying heat and optionally a vacuum, and permitting the conducting polymer to self-assemble into an organic semiconductor. The organic semiconductor can be employed within single and multi-cell memory devices by forming a structure with two or more electrodes while employing the organic semiconductor along with a passive device between the electrodes. A partitioning component can be integrated with the memory device to facilitate programming and stacking of additional memory cells on top of or in association with previously formed cells.
摘要翻译：本发明提供可用作存储单元的选择性导电的有机半导体（例如，聚合物）器件。包括导电聚合物的聚合物溶液相对于导电电极自组装。该过程提供自组装，使得可以实现最短的导电路径。该方法包括将导电聚合物的浓缩溶液沉积在导电表面上，施加热量和任选的真空，并允许导电聚合物自组装成有机半导体。有机半导体可以在单电池和多电池存储器件中使用，通过形成具有两个或多个电极的结构，同时在电极之间使用有机半导体以及无源器件。分区组件可以与存储器件集成，以便于在先前形成的单元之上或与之前相关联的附加存储器单元的编程和堆叠。

46. 发明授权

US06579778B1 Source bus formation for a flash memory using silicide 有权
标题翻译：用于使用硅化物的闪存的源总线形成
公开(公告)号：US06579778B1
公开(公告)日：2003-06-17
申请号：US09634991
申请日：2000-08-08
申请人： Nicholas H. Tripsas , Mark Ramsbey
发明人： Nicholas H. Tripsas , Mark Ramsbey
IPC分类号： H01L2176
CPC分类号： H01L27/11521 , H01L27/115
摘要： A semiconductor flash memory device is formed with shallow trench isolation (STI) and a low-resistance source bus line (Vss Bus). Embodiments include forming core and peripheral field oxide regions, as by conventional STI techniques, bit lines by ion implantation, polysilicon floating gates above the channel regions and polysilicon word lines. The Vss Bus is then formed by etching away portions of the field oxide between corresponding source regions of adjacent bit lines to expose portions of the substrate, ion implanting impurities into the source regions and the exposed substrate, forming insulating spacers on the sides of the floating gates and word lines, and forming a metal silicide layer, such as titanium silicide, on the implanted source regions and exposed portions of the substrate to form a continuous conductor between the source regions. The metal silicide layer provides a low-resistance Vss, thereby improving device performance, while the implanted impurities ensure that the substrate will not short circuit to source and drain regions through the metal silicide.
摘要翻译：半导体闪速存储器件形成有浅沟槽隔离（STI）和低电阻源总线（Vss Bus）。实施例包括如常规STI技术形成核心和外围场氧化物区域，通过离子注入的位线，在沟道区域上方的多晶硅浮动栅极和多晶硅字线。然后通过蚀刻除去相邻位线的相应源极区域之间的场氧化物的部分以暴露衬底的部分，离子将杂质注入到源极区域和暴露的衬底中，形成Vss母线，在浮动的侧面上形成绝缘衬垫栅极和字线，以及在注入的源极区域和衬底的暴露部分上形成诸如硅化钛的金属硅化物层，以在源极区域之间形成连续的导体。金属硅化物层提供低电阻Vss，从而提高器件性能，而注入的杂质确保衬底不会通过金属硅化物短路到源极和漏极区。

47. 发明授权

US6153487A Approach for the formation of semiconductor devices which reduces band-to-band tunneling current and short-channel effects 失效
标题翻译：用于形成减少带对隧道电流和短沟道效应的半导体器件的方法
公开(公告)号：US6153487A
公开(公告)日：2000-11-28
申请号：US40107
申请日：1998-03-17
申请人： Scott D. Luning , Timothy J. Thurgate , Daniel Sobek , Nicholas H. Tripsas
发明人： Scott D. Luning , Timothy J. Thurgate , Daniel Sobek , Nicholas H. Tripsas
IPC分类号： H01L21/265 , H01L21/336 , H01L21/22 , H01L21/38 , H01L29/76
CPC分类号： H01L29/66825 , H01L21/2652
摘要： The present invention provides a method and system for the formation of semiconductor devices which reduces band-to-band tunneling current and short-channel effects. The method and system includes implanting first low-dose arsenic into an area in the substrate, thermally diffusing the first low-dose arsenic through a portion of the substrate, implanting a second higher-dose arsenic into the area in the substrate, and diffusing the second higher-dose arsenic into the area in the substrate. Under the present invention, the combination of the first and second arsenic implants has a graded lateral profile which reduces band-to-band tunneling current and short-channel effects. The method also improves the reliability and performance of the semiconductor devices.
摘要翻译：本发明提供一种用于形成半导体器件的方法和系统，其减少带间隧穿电流和短沟道效应。该方法和系统包括将第一低剂量砷注入到衬底中的区域中，通过衬底的一部分热扩散第一低剂量砷，将第二较高剂量的砷注入到衬底的区域中，第二高剂量砷进入底物区域。在本发明中，第一和第二砷植入物的组合具有梯度横向轮廓，其降低带对隧道电流和短通道效应。该方法还提高了半导体器件的可靠性和性能。

48. 发明授权

US5789802A Dopant profile spreading for arsenic source/drain 失效
标题翻译：砷源/漏极的掺杂分布扩散
公开(公告)号：US5789802A
公开(公告)日：1998-08-04
申请号：US667570
申请日：1996-06-21
申请人： Nicholas H. Tripsas
发明人： Nicholas H. Tripsas
IPC分类号： H01L21/265 , H01L21/8234 , H01L29/08 , H01L29/45 , H01L29/67 , H01L29/76 , H01L29/94
CPC分类号： H01L21/2652 , H01L21/823418 , H01L29/0847 , H01L29/456 , B26F1/384
摘要： An improved process for forming shallow arsenic-doped source/drain regions in MOS devices utilizes a two-step arsenic implant which lowers the surface arsenic concentration while maintaining sharp junction profile and desired junction depth. Minimizing the excess arsenic in the surface region improves silicidation characteristics.
摘要翻译：用于在MOS器件中形成浅砷掺杂源/漏区的改进方法利用两步砷注入，其降低表面砷浓度，同时保持尖锐的结形态和期望的结深度。使表面区域中的过量砷最小化提高了硅化物的特性。

49. 发明授权

US08012673B1 Processing a copolymer to form a polymer memory cell 有权
标题翻译：加工共聚物以形成聚合物记忆体
公开(公告)号：US08012673B1
公开(公告)日：2011-09-06
申请号：US11068674
申请日：2005-03-01
申请人： Suzette K. Pangrle , Matthew S. Buynoski , Nicholas H. Tripsas , Uzodinma Okoroanyanwu
发明人： Suzette K. Pangrle , Matthew S. Buynoski , Nicholas H. Tripsas , Uzodinma Okoroanyanwu
IPC分类号： H01L21/02
CPC分类号： H01L27/285 , H01L51/0035 , H01L51/004
摘要： Disclosed are organic semiconductor devices containing a copolymer layer that contains a polymer dielectric and a semiconducting polymer formed using actinic radiation. As initially formed, the copolymer layer has dielectric properties, but portions may selectively rendered conductive after those portions are exposed to actinic radiation. Also disclosed are methods of making the organic semiconductor devices. Such devices are characterized by light weight and robust reliability.
摘要翻译：公开了包含含有聚合物电介质和使用光化辐射形成的半导体聚合物的共聚物层的有机半导体器件。如最初形成的那样，共聚物层具有介电性质，但是在这些部分暴露于光化辐射之后，部分可以选择性地导电。还公开了制造有机半导体器件的方法。这样的装置的特征在于重量轻和鲁棒的可靠性。

50. 发明授权

US08003436B2 Stacked organic memory devices and methods of operating and fabricating 有权
标题翻译：堆叠有机存储器件及其操作和制造方法
公开(公告)号：US08003436B2
公开(公告)日：2011-08-23
申请号：US12327040
申请日：2008-12-03
申请人： Nicholas H. Tripsas , Uzodinma Okoroanyanwu , Suzette K. Pangrle , Michael A. VanBuskirk
发明人： Nicholas H. Tripsas , Uzodinma Okoroanyanwu , Suzette K. Pangrle , Michael A. VanBuskirk
IPC分类号： H01L51/00
CPC分类号： G11C13/0014 , B82Y10/00 , G11C11/5664 , G11C13/0016 , H01L27/28 , H01L51/0035 , H01L51/0036 , H01L51/0038 , H01L51/0041 , H01L51/0077 , H01L51/0078
摘要： The present invention provides a multi-layer organic memory device that can operate as a non-volatile memory device having a plurality of stacked and/or parallel memory structures constructed therein. A multi-cell and multi-layer organic memory component can be formed with two or more electrodes having a selectively conductive media between the electrodes forming individual cells, while utilizing a partitioning component to enable stacking of additional memory cells on top of or in association with previously formed cells. Memory stacks can be formed by adding additional layers—respective layers separated by additional partitioning components, wherein multiple stacks can be formed in parallel to provide a high-density memory device.
摘要翻译：本发明提供一种多层有机存储器件，其可以作为其中构造有多个堆叠和/或并行存储器结构的非易失性存储器件来操作。可以在两个或多个电极之间形成多单元和多层有机存储器组件，所述两个或更多个电极在形成各个单元的电极之间具有选择性导电介质，同时利用分隔组件使得能够堆叠额外的存储器单元，以前形成的细胞。可以通过添加额外的层 - 通过附加分隔部件分开的相应层来形成存储器堆叠，其中可以并行形成多个堆叠以提供高密度存储器件。

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