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41. 发明申请

US20050247922A1 Phase random access memory with high density 有权
标题翻译：高密度相位随机存取存储器
公开(公告)号：US20050247922A1
公开(公告)日：2005-11-10
申请号：US11177115
申请日：2005-07-08
申请人： Hyung-Rok Oh , Beak-Hyung Cho , Du-Eung Kim , Woo-Yeong Cho
发明人： Hyung-Rok Oh , Beak-Hyung Cho , Du-Eung Kim , Woo-Yeong Cho
IPC分类号： G11C13/00 , G11B7/24 , G11C11/56 , G11C16/02 , H01L27/10 , H01L27/105 , H01L27/24 , H01L29/76 , H01L45/00 , H01L47/00
CPC分类号： G11C13/0004 , G11C11/5678 , G11C2213/79 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/122 , H01L45/144
摘要： A phase random access memory including a plurality of access transistors, each access transistor including a drain region, and a phase-changeable film shared by the plurality of access transistors. The phase-changeable film is connected to a bitline through a first electrode and connected to each respective drain region through at least one of a plurality of second electrodes.
摘要翻译：一种包括多个存取晶体管的相位随机存取存储器，每个存取晶体管包括漏极区域，以及由多个存取晶体管共享的可相位改变的薄膜。相变膜通过第一电极连接到位线，并通过多个第二电极中的至少一个连接到每个相应的漏极区域。

42. 发明授权

US06928022B2 Write driver circuit in phase change memory device and method for applying write current 有权
标题翻译：在相变存储器件中写入驱动电路以及施加写入电流的方法
公开(公告)号：US06928022B2
公开(公告)日：2005-08-09
申请号：US10969697
申请日：2004-10-20
申请人： Beak-Hyung Cho , Choong-Keun Kwak
发明人： Beak-Hyung Cho , Choong-Keun Kwak
IPC分类号： G11C13/02 , G11C13/00 , G11C16/02 , G11C16/12 , G11C16/30 , G11C29/02 , H01L27/105 , H01L45/00 , G11C17/18
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0038 , G11C29/02 , G11C29/028 , G11C2013/0078 , G11C2029/5006 , G11C2213/79
摘要： A write driver circuit including a plurality of programmable fuses for a phase change memory device in which a write operation is correctly performed even in the case where a current output shift in a write current generation circuit; or in the case where a phase change memory cell having a phase change property shift due to an external factor or due a process change. The write driver circuit includes a write current control unit for outputting a first or second level of voltage selected, by selecting one of a first or second programmable current path, based on whether a first or second selection pulse signal is applied; and a current driving unit for generating a write current controlled by the output voltage of the write current control unit. Each of the first and second programmable current paths includes fuses that can be programmed to adjust their resistance to adjust the respective selected output voltage to compensate for the current output shift in the write current generation circuit or for the phase change memory cell having the phase change property shift.
摘要翻译：一种写入驱动器电路，包括用于相变存储器件的多个可编程保险丝，其中即使在写入电流产生电路中的电流输出移位的情况下也正确地执行写入操作; 或者由于外部因素或由于处理变化而具有相变特性偏移的相变存储单元的情况。写入驱动器电路包括：写入电流控制单元，用于通过选择第一或第二可选择电流路径中的一个，基于是否应用第一或第二选择脉冲信号来输出所选择的第一或第二电平电平; 以及电流驱动单元，用于产生由写入电流控制单元的输出电压控制的写入电流。第一和第二可编程电流路径中的每一个包括熔丝，其可以被编程以调整其电阻以调整相应的选择的输出电压以补偿写入电流产生电路中的电流输出偏移或具有相变的相变存储器单元财产转移

43. 发明授权

US07994493B2 Phase change memory devices employing cell diodes and methods of fabricating the same 有权
标题翻译：使用单元二极管的相变存储器件及其制造方法
公开(公告)号：US07994493B2
公开(公告)日：2011-08-09
申请号：US12196137
申请日：2008-08-21
申请人： Woo-Yeong Cho , Du-Eung Kim , Yun-Seung Shin , Hyun-Geun Byun , Sang-Beom Kang , Beak-Hyung Cho , Choong-Keun Kwak
发明人： Woo-Yeong Cho , Du-Eung Kim , Yun-Seung Shin , Hyun-Geun Byun , Sang-Beom Kang , Beak-Hyung Cho , Choong-Keun Kwak
IPC分类号： H01L29/04 , H01L47/00
CPC分类号： G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： Phase change memory devices may include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate. The word lines may have a second conductivity type different from the first conductivity type and substantially flat top surfaces. First and second semiconductor patterns may be sequentially stacked on each word line, and an insulating layer may be provided to fill gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns. A plurality of phase change material patterns may be two-dimensionally arrayed on the insulating layer and electrically connected to the second semiconductor patterns.
摘要翻译：相变存储器件可以包括第一导电类型的半导体衬底和设置在半导体衬底上的多个平行字线。字线可以具有不同于第一导电类型和基本上平坦的顶表面的第二导电类型。第一和第二半导体图案可以顺序地堆叠在每个字线上，并且可以提供绝缘层以填充字线之间的间隙区域，第一半导体图案之间的间隙区域和第二半导体图案之间的间隙区域。多个相变材料图案可以二维排列在绝缘层上并电连接到第二半导体图案。

44. 发明申请

US20110188303A1 Phase change memory device generating program current and mehtod thereof 有权
标题翻译：相变存储器件产生程序电流和电流
公开(公告)号：US20110188303A1
公开(公告)日：2011-08-04
申请号：US13064672
申请日：2011-04-07
申请人： Beak-Hyung Cho , Woo-Yeong Cho , Mu-Hui Park
发明人： Beak-Hyung Cho , Woo-Yeong Cho , Mu-Hui Park
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0078 , G11C2013/0092 , G11C2213/72
摘要： A phase change memory device may include a memory cell array, a write driver, and/or a control unit. The memory cell array may include a plurality of memory cells. The write driver may be configured to provide a program current to the memory cell array for setting a state of a phase change material to program a selected memory cell. The write driver may be configured to provide the program current such that the program current has a plurality of steps. The control unit may be configured to receive step information for adjusting a magnitude and a width of each step of the program current during a test operation and provide the step information to the write driver during a normal operation.
摘要翻译：相变存储器件可以包括存储单元阵列，写入驱动器和/或控制单元。存储单元阵列可以包括多个存储单元。写入驱动器可以被配置为向存储器单元阵列提供程序电流，用于设置相变材料的状态以对选定的存储单元进行编程。写驱动器可以被配置为提供程序电流，使得程序电流具有多个步骤。控制单元可以被配置为在测试操作期间接收用于调整程序电流的每个步骤的幅度和宽度的步骤信息，并且在正常操作期间将该步骤信息提供给写入驱动器。

45. 发明授权

US07936612B2 Phase change memory device generating program current and method thereof 有权
标题翻译：相变存储器件产生程序电流及其方法
公开(公告)号：US07936612B2
公开(公告)日：2011-05-03
申请号：US12654338
申请日：2009-12-17
申请人： Beak-Hyung Cho , Woo-Yeong Cho , Mu-Hui Park
发明人： Beak-Hyung Cho , Woo-Yeong Cho , Mu-Hui Park
IPC分类号： G11C7/10
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0078 , G11C2013/0092 , G11C2213/72
摘要： A phase change memory device may include a memory cell array, a write driver, and/or a control unit. The memory cell array may include a plurality of memory cells. The write driver may be configured to provide a program current to the memory cell array for setting a state of a phase change material to program a selected memory cell. The write driver may be configured to provide the program current such that the program current has a plurality of steps. The control unit may be configured to receive step information for adjusting a magnitude and a width of each step of the program current during a test operation and provide the step information to the write driver during a normal operation.
摘要翻译：相变存储器件可以包括存储单元阵列，写入驱动器和/或控制单元。存储单元阵列可以包括多个存储单元。写入驱动器可以被配置为向存储器单元阵列提供程序电流，用于设置相变材料的状态以对选定的存储单元进行编程。写驱动器可以被配置为提供程序电流，使得程序电流具有多个步骤。控制单元可以被配置为在测试操作期间接收用于调整程序电流的每个步骤的幅度和宽度的步骤信息，并且在正常操作期间将该步骤信息提供给写入驱动器。

46. 发明授权

US07889548B2 Method for reducing a reset current for resetting a portion of a phase change material in a memory cell of a phase change memory device and the phase change memory device 有权
标题翻译：减少用于复位相变存储器件和相变存储器件的存储单元中的相变材料的一部分的复位电流的方法
公开(公告)号：US07889548B2
公开(公告)日：2011-02-15
申请号：US12585637
申请日：2009-09-21
申请人： Chang-Wook Jeong , Jun-Hyok Kong , Ji-Hye Yi , Beak-Hyung Cho
发明人： Chang-Wook Jeong , Jun-Hyok Kong , Ji-Hye Yi , Beak-Hyung Cho
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C2013/0083 , Y10S977/754
摘要： According to one embodiment, at least a portion of the phase change material including a first crystalline phase is converted to one of a second crystalline phase and an amorphous phase. The second crystalline phase transitions to the amorphous phase more easily than the first crystalline phase. For example, the first crystalline phase may be a hexagonal closed packed structure, and the first crystalline phase may be a face centered cubic structure.
摘要翻译：根据一个实施方案，包括第一结晶相的至少一部分相变材料转化为第二结晶相和非晶相之一。第二结晶相比第一结晶相更容易转变成非晶态。例如，第一结晶相可以是六方密封填充结构，并且第一结晶相可以是面心立方结构。

47. 发明授权

US07710767B2 Memory cell array biasing method and a semiconductor memory device 有权
标题翻译：存储单元阵列偏置方法和半导体存储器件
公开(公告)号：US07710767B2
公开(公告)日：2010-05-04
申请号：US11969326
申请日：2008-01-04
申请人： Beak-Hyung Cho , Do-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
发明人： Beak-Hyung Cho , Do-Eung Kim , Choong-Keun Kwak , Sang-Beom Kang , Woo-Yeong Cho , Hyung-Rok Oh
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C13/0004 , G11C13/0069 , G11C2013/009 , G11C2213/72
摘要： A method of biasing a memory cell array during a data writing operation and a semiconductor memory device, in which the semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is connected to a corresponding first line among a plurality of first lines and a second terminal of a memory cell is connected to a corresponding second line among a plurality of second lines; and a bias circuit for biasing a selected second line to a first voltage and non-selected second lines to a second voltage.
摘要翻译：一种在数据写入操作期间偏置存储单元阵列的方法和半导体存储器件，其中半导体存储器件包括：存储单元阵列，其包括多个存储单元，其中存储单元的第一端子连接到多个第一行中的对应的第一行和存储单元的第二端连接到多条第二行中的对应的第二行; 以及用于将所选择的第二线偏压到第一电压和未选择的第二线到第二电压的偏置电路。

48. 发明申请

US20100097850A1 APPARATUS AND SYSTEMS USING PHASE CHANGE MEMORIES 有权
标题翻译：使用相变记忆的装置和系统
公开(公告)号：US20100097850A1
公开(公告)日：2010-04-22
申请号：US12611606
申请日：2009-11-03
申请人： Beak-Hyung Cho , Du-Eung Kim , Woo-Yeong Cho
发明人： Beak-Hyung Cho , Du-Eung Kim , Woo-Yeong Cho
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0078 , G11C2013/0092
摘要： Apparatus and systems that use phase-change memory devices are provided. The phase-change memory devices may include multiple phase-change memory cells and a reset pulse generation circuit configured to output multiple sequential reset pulses. Each sequential reset pulse is output to a corresponding one of multiple reset lines. Multiple write driver circuits are coupled to corresponding phase change memory cells and to a corresponding one of the reset lines of the reset pulse generation circuit.
摘要翻译：提供了使用相变存储器件的装置和系统。相变存储器件可以包括多个相变存储器单元和被配置为输出多个顺序复位脉冲的复位脉冲发生电路。每个顺序复位脉冲被输出到多个复位线中相应的一个。多个写入驱动器电路耦合到相应的相变存储器单元和复位脉冲发生电路的相应的一个复位线。

49. 发明授权

US07668007B2 Memory system including a resistance variable memory device 有权
标题翻译：存储器系统包括电阻变量存储器件
公开(公告)号：US07668007B2
公开(公告)日：2010-02-23
申请号：US12124523
申请日：2008-05-21
申请人： Byung-Gil Choi , Woo-Yeong Cho , Du-Eung Kim , Hyung-Rok Oh , Beak-Hyung Cho , Yu-Hwan Ro
发明人： Byung-Gil Choi , Woo-Yeong Cho , Du-Eung Kim , Hyung-Rok Oh , Beak-Hyung Cho , Yu-Hwan Ro
IPC分类号： G11C11/00
CPC分类号： G11C8/10 , G11C13/0004 , G11C13/004 , G11C2013/0054 , G11C2213/72
摘要： A memory system includes a resistance variable memory device, and a memory controller for controlling the resistance variable memory device. The resistance variable memory device includes a memory cell connected to a bitline, a high voltage circuit adapted to generate a high voltage from an externally provided power source voltage, where the high voltage is higher than the power source voltage, a precharging circuit adapted to charge the bitline to the power source voltage and further charge the bitline to the high voltage, a bias circuit adapted to provide a read current to the bitline with using the high voltage, and a sense amplifier adapted to detect a voltage level of the bitline with using the high voltage.
摘要翻译：存储器系统包括电阻可变存储器件和用于控制电阻变化存储器件的存储器控制器。电阻可变存储器件包括连接到位线的存储单元，适于从外部提供的电源电压产生高电压的高压电路，其中高电压高于电源电压，预充电电路适于充电位线到电源电压并进一步将位线充电到高电压，偏置电路适于使用高电压向位线提供读取电流;以及读出放大器，其适于使用来检测位线的电压电平高电压。

50. 发明申请

US20090316474A1 Phase change memory 有权
标题翻译：相变记忆
公开(公告)号：US20090316474A1
公开(公告)日：2009-12-24
申请号：US12457319
申请日：2009-06-08
申请人： Beak-Hyung Cho , Byung-Gil Choi , Joon-Min Park
发明人： Beak-Hyung Cho , Byung-Gil Choi , Joon-Min Park
IPC分类号： G11C11/00 , G11C29/00
CPC分类号： G11C29/808 , G11C13/0004
摘要： The phase change memory device includes a plurality of memory banks, a plurality of local conductor lines connected to the plurality of memory banks, at least one global conductor line connected to the plurality of local conductor lines, and at least one repair control circuit configured to selectively replace at least one of the at least one global conductor line with at least one redundant global conductor line and configured to selectively replace at least one of the plurality of local conductor lines with at least one redundant local conductor line.
摘要翻译：所述相变存储器件包括多个存储体，连接到所述多个存储体的多个局部导体线，连接到所述多个局部导体线的至少一个全局导体线，以及至少一个修理控制电路，选择性地将所述至少一个全局导体线中的至少一个与至少一个冗余全局导体线替换并且被配置为用至少一个冗余局部导体线选择性地替换所述多条局部导体线中的至少一个。

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