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41. 发明申请

US20050285124A1 Micro or below scale multi-layered heteostructure 有权
标题翻译：微量或低于尺度的多层结构
公开(公告)号：US20050285124A1
公开(公告)日：2005-12-29
申请号：US10879390
申请日：2004-06-29
申请人： Jun-Fei Zheng
发明人： Jun-Fei Zheng
IPC分类号： H01L23/31 , H01L29/06 , H01L29/22 , H01L31/0352 , H01L31/105
CPC分类号： H01L23/3185 , H01L29/0657 , H01L31/0352 , H01L31/105 , H01L2924/0002 , H01L2924/00
摘要： A heteostructure having a first and a second layer, in micrometer or smaller (e.g. nanometer) scale, arranged in a configuration defining at least one undercut at one side of the second layer, underneath the first layer, is described herein. In various embodiments, the undercut is filled with passivation materials to protect the layers underneath the first layer. Further, in various embodiments, a large metal contact layer including coverage of the first layer sidewall may be employed to provide significant increase in contact area, and to reduce the device contact resist value.
摘要翻译：在本文中描述了具有在微米或更小（例如纳米））刻度的第一和第二层的整体结构，其布置成在第一层下方限定在第二层的一侧的至少一个底切的构型。在各种实施例中，底切部分填充有钝化材料以保护第一层下方的层。此外，在各种实施例中，可以使用包括第一层侧壁的覆盖层的大的金属接触层来提供接触面积的显着增加，并且减小器件接触抗蚀剂值。

42. 发明申请

US20050069258A1 Optical waveguide Y-branch splitter 失效
标题翻译：光波导Y分支分路器
公开(公告)号：US20050069258A1
公开(公告)日：2005-03-31
申请号：US10675148
申请日：2003-09-29
申请人： Jun-Fei Zheng , Christina Manolatou , Kazumi Wada
发明人： Jun-Fei Zheng , Christina Manolatou , Kazumi Wada
IPC分类号： G02B6/125 , G02B6/28 , G02B6/26 , G02B6/42
CPC分类号： G02B6/2804 , G02B6/125
摘要： A method and apparatus for splitting/coupling optical signal(s). A unitary waveguide section having a first lateral dimension perpendicular to a propagation axis of the unitary section is provided. An offset waveguide section is optically coupled to the unitary waveguide section. The offset waveguide section has a second lateral dimension approximately equal to twice the first lateral dimension. Two branching waveguide sections having first ends are optically coupled to the offset section at the first ends.
摘要翻译：一种用于分离/耦合光信号的方法和装置。提供了具有垂直于整体部分的传播轴的第一横向尺寸的单一波导部分。偏移波导部分光耦合到单一波导部分。偏移波导部分具有大致等于第一横向尺寸的两倍的第二横向尺寸。具有第一端的两个分支波导部分在第一端处光耦合到偏移部分。

43. 发明授权

US06846740B2 Wafer-level quasi-planarization and passivation for multi-height structures 失效
标题翻译：多高度结构的晶圆级准平面化和钝化
公开(公告)号：US06846740B2
公开(公告)日：2005-01-25
申请号：US10460880
申请日：2003-06-14
申请人： Hilmi Volkan Demir , Onur Fidaner , David Andrew Barclay Miller , Vijit Sabnis , Jun-Fei Zheng
发明人： Hilmi Volkan Demir , Onur Fidaner , David Andrew Barclay Miller , Vijit Sabnis , Jun-Fei Zheng
IPC分类号： H01L21/3105 , H01L21/336 , H01L21/44 , H01L21/4763 , H01L21/768 , H01L21/3202
CPC分类号： H01L21/76819 , H01L21/31058
摘要： Methods in accordance with the present invention provide a quasi-planarized surface between one or more semiconductor devices and at least a portion of surrounding passivation material, where the devices have different elevations above a substrate. A hard mask defines the planarized surface as the interface between the hard mask and both the passivation layer and the device, after a passivation layer etching process. The resulting planarized surface has a small to zero step height, is insensitive to passivation layer non-uniformity and etch non-uniformity, provides full passivation of the device side wall, provides protection for the device against etch-induced damage, and prevents the detrimental effects of passivation layer voids. The methods are applicable to semiconductor device fabrication for electronic and photonic/optoelectronic systems such as, but not limited to, cell phones, networking systems, high brightness (HB) LEDs, laser diodes (LDs), photodiodes, modulator diodes and multifunction solar cells.
摘要翻译：根据本发明的方法提供一个或多个半导体器件与周围钝化材料的至少一部分之间的准平面化表面，其中器件在衬底之上具有不同的高度。在钝化层蚀刻工艺之后，硬掩模将平坦化表面定义为硬掩模与钝化层和器件之间的界面。所得到的平坦化表面具有小至零的阶梯高度，对钝化层不均匀性和蚀刻不均匀性不敏感，提供器件侧壁的完全钝化，为器件提供防蚀蚀引起的损伤的保护，并防止有害的钝化层空隙的影响。该方法适用于电子和光子/光电子系统的半导体器件制造，例如但不限于蜂窝电话，网络系统，高亮度（HB）LED，激光二极管（LD），光电二极管，调制二极管和多功能太阳能电池。

44. 发明授权

US06806204B1 Semiconductor etch speed modification 有权
标题翻译：半导体蚀刻速度修改
公开(公告)号：US06806204B1
公开(公告)日：2004-10-19
申请号：US10611837
申请日：2003-06-30
申请人： Jun-Fei Zheng , Jesper Hanberg
发明人： Jun-Fei Zheng , Jesper Hanberg
IPC分类号： H01L21302
CPC分类号： H01L21/3081 , H01L21/30612
摘要： In accordance with embodiments of the methods of the present invention, a sacrificial layer provides an etch speed modification to effectively etch multiple semiconductor devices having dissimilar materials to a common layer or substrate with a common etch process. The time to etch remove a second exposed portion is compared with the time to etch remove a first exposed portion, and a sacrificial layer is deposited on the first exposed portion having a time to etch remove substantially equal to the difference. The sacrificial layer is provided to have predetermined material composition, material property and layer thickness, among other things, to provide a desired time to etch remove. The methods also provide for self-aligned via formation providing highly defined vias by the etch removal of sacrificial material rather than direct etching of the vie. The methods also provide planarization between two or more devices.
摘要翻译：根据本发明的方法的实施例，牺牲层提供蚀刻速度修改以通过公共蚀刻工艺有效地将具有不同材料的多个半导体器件蚀刻到公共层或衬底。将蚀刻去除第二暴露部分的时间与蚀刻时间相比较去除第一暴露部分，并且牺牲层沉积在第一暴露部分上，其蚀刻时间基本上等于该差异。提供牺牲层以具有预定的材料组成，材料性质和层厚度，以提供蚀刻去除所需的时间。这些方法还提供了自对准通孔形成，通过蚀刻去除牺牲材料而不是直接蚀刻，提供高度限定的通孔。这些方法还提供两个或多个设备之间的平坦化。

45. 发明授权

US06794232B2 Method of making MOSFET gate electrodes with tuned work function 有权
标题翻译：制造具有调谐功能的MOSFET栅电极的方法
公开(公告)号：US06794232B2
公开(公告)日：2004-09-21
申请号：US10383842
申请日：2003-03-07
申请人： Jun-Fei Zheng , Brian Doyle , Gang Bai , Chunlin Liang
发明人： Jun-Fei Zheng , Brian Doyle , Gang Bai , Chunlin Liang
IPC分类号： H01I21337
CPC分类号： H01L21/82345 , H01L21/823425 , H01L27/088
摘要： Insulated gate field effect transistors having gate electrodes with at least two layers of materials provide gate electrode work function values that are similar to those of doped polysilicon, eliminate the poly depletion effect and also substantially prevent impurity diffusion into the gate dielectric. Bi-layer stacks of relatively thick Al and thin TiN for n-channel FETs and bi-layer stacks of relatively thick Pd and thin TiN, or relatively thick Pd and thin TaN for p-channel FETs are disclosed. Varying the thickness of the thin TiN or TaN layers between a first and second critical thickness may be used to modulate the work function of the gate electrode and thereby obtain the desired trade-off between channel doping and drive currents in FETs.
摘要翻译：具有至少两层材料的栅电极的绝缘栅场效应晶体管提供类似于掺杂多晶硅的栅电极功函数值，消除多余耗效应并且还基本上防止杂质扩散入栅电介质。公开了用于n沟道FET的相对厚的Al和薄TiN的双层堆叠以及相对厚的Pd和薄TiN的双层堆叠，或者用于p沟道FET的相对厚的Pd和薄TaN。改变第一和第二临界厚度之间的薄TiN或TaN层的厚度可以用于调制栅电极的功函数，从而在FET中的沟道掺杂和驱动电流之间获得期望的权衡。

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