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41. 发明授权

US06883072B2 Memory system and method of using same 有权
标题翻译：内存系统及其使用方法
公开(公告)号：US06883072B2
公开(公告)日：2005-04-19
申请号：US10408383
申请日：2003-04-07
申请人： John K. Walton , Christopher S. MacLellan
发明人： John K. Walton , Christopher S. MacLellan
IPC分类号： G06F3/06 , G06F12/00
CPC分类号： G06F3/061 , G06F3/0655 , G06F3/067
摘要： A memory system and method of using same are provided. In one embodiment of the present invention, the memory system may include a plurality of logic sections that may be used to facilitate execution of relatively complex atomic read-modify-write operations.
摘要翻译：提供了一种存储系统及其使用方法。在本发明的一个实施例中，存储器系统可以包括多个逻辑部分，其可以用于促进相对复杂的原子读取 - 修改 - 写入操作的执行。

42. 发明授权

US06779150B1 CRC error detection system and method 有权
标题翻译： CRC错误检测系统和方法
公开(公告)号：US06779150B1
公开(公告)日：2004-08-17
申请号：US09745573
申请日：2000-12-21
申请人： John K. Walton , Christopher S. MacLellan
发明人： John K. Walton , Christopher S. MacLellan
IPC分类号： G11C2900
CPC分类号： G06F11/1004
摘要： A method and system for protecting erroneous data from being stored in a memory, such DATA comprising a series of data words terminating in a Cyclic Redundancy Check (CRC). The method includes: checking the CRC of the data words while delaying the DATA from passing to an output; corrupting the delayed data words if such checking determines a CRC error, such corruption of one of the data words being performed prior to the data words pass to said output; detecting whether such data word at the output is corrupt; and inhibiting storage of such data words in the memory if such one of the data words at the output is detected as being corrupt.
摘要翻译：一种用于保护错误数据不被存储在存储器中的方法和系统，所述数据包括终止于循环冗余校验（CRC）的一系列数据字。该方法包括：在将DATA传送到输出的同时，检查数据字的CRC; 如果这种检查确定CRC错误，则破坏延迟的数据字，在数据字传递到所述输出之前执行的数据字之一的这种损坏; 检测输出中的这种数据字是否损坏; 并且如果检测到输出处的这些数据字被破坏，则将这种数据字存储在存储器中。

43. 发明授权

US06609185B1 Data storage system having majority gate filter 有权
标题翻译：数据存储系统具有多数门极滤波器
公开(公告)号：US06609185B1
公开(公告)日：2003-08-19
申请号：US09859605
申请日：2001-05-17
申请人： John K. Walton
发明人： John K. Walton
IPC分类号： G06F1200
CPC分类号： G06F11/183 , G06F3/0601 , G06F11/004 , G06F11/0796 , G06F11/2005 , G06F11/2089 , G06F2003/0692
摘要： An arbitration system having a common resource and a first arbitration logic. The first arbitration logic includes a plurality of logic sections. Each one of the logic sections is fed a corresponding one of a plurality of request signals for the common resource. The logic sections produce, in response to request signals, a corresponding one of a plurality of grant signals. Each one of such sections has: a corresponding one of a plurality of first data storage elements, each one of such storage elements storing a corresponding one of the grant signals in response to first clock pulses, such stored grant signals being provided at outputs of the storage elements. The arbitration system includes a plurality of transmission channels, each one having an input coupled to a corresponding one of the outputs of the plurality of first data storage elements. The plurality of transmission channels pass the grant signals stored in the first data storage elements to outputs of the transmission channels. Also provided is a second arbitration logic. The second arbitration logic includes a second plurality of data storage elements, each one thereof having an input coupled to an output of a corresponding one of the transmission channels. The grant signals at the outputs of the channels are stored in the second plurality of storage elements in response to clock pulses from a second source of clock pulse. The clock pulses produced by the first source of clock pulses are independent of the clock pulses produced by the second source of clock pulses. The second arbitration logic also includes a plurality of majority gates. Each one of the gates has a plurality of inputs. Each one of such plurality of inputs is coupled to an output of each of the second plurality of data storage elements. Each one of the majority gates produces an output in accordance with a majority of the data fed thereto.
摘要翻译：具有公共资源和第一仲裁逻辑的仲裁系统。第一仲裁逻辑包括多个逻辑部分。每个逻辑部分馈送用于公共资源的多个请求信号中的相应一个。逻辑部分响应于请求信号产生多个授权信号中的对应的一个。这些部分中的每一个具有：多个第一数据存储元件中的相应一个，这些存储元件中的每一个响应于第一时钟脉冲而存储相应的一个授权信号，这样的存储的授权信号被提供在存储元件。仲裁系统包括多个传输信道，每个传输信道具有耦合到多个第一数据存储元件的相应输出端的输入端。多个传输信道将存储在第一数据存储元件中的授权信号传递到传输信道的输出。还提供了第二仲裁逻辑。第二仲裁逻辑包括第二多个数据存储元件，其中每一个具有耦合到相应一个传输通道的输出的输入。响应于来自第二时钟脉冲源的时钟脉冲，在通道的输出处的授权信号被存储在第二多个存储元件中。由第一时钟脉冲源产生的时钟脉冲与由第二时钟脉冲源产生的时钟脉冲无关。第二仲裁逻辑还包括多个多数门。每个门都有多个输入。这些多个输入中的每一个耦合到第二多个数据存储元件中的每一个的输出。多数门中的每一个根据馈送给其的大部分数据产生输出。

44. 发明授权

US06578126B1 Memory system and method of using same 有权
标题翻译：内存系统及其使用方法
公开(公告)号：US06578126B1
公开(公告)日：2003-06-10
申请号：US09960177
申请日：2001-09-21
申请人： Christopher S. MacLellan , John K. Walton
发明人： Christopher S. MacLellan , John K. Walton
IPC分类号： G06F1200
CPC分类号： G06F13/4243
摘要： A memory system and method of using same are provided. In one embodiment of the present invention, a novel memory operation protocol may be used to facilitate the execution of memory operations in the memory system. These memory operations may include atomic read-modify-write operations that may involve arithmetic and/or logical operations of greater complexity than those that may be carried out in the prior art.
摘要翻译：提供了一种存储系统及其使用方法。在本发明的一个实施例中，可以使用新的存储器操作协议来促进存储器系统中的存储器操作的执行。这些存储器操作可以包括原子读取 - 修改 - 写入操作，其可以涉及比现有技术中可能执行的更复杂的算术和/或逻辑运算。

45. 发明授权

US06249878B1 Data storage system 失效
标题翻译：数据存储系统
公开(公告)号：US06249878B1
公开(公告)日：2001-06-19
申请号：US09052113
申请日：1998-03-31
申请人： Christopher S. MacLellan , John K. Walton
发明人： Christopher S. MacLellan , John K. Walton
IPC分类号： G06F1110
CPC分类号： G06F11/183 , G06F11/1625 , G06F12/0866
摘要： A data storage system having a plurality of addressable memories for storing a global variable. Each one of a plurality of controllers is adapted to request an operation on first and second data stored in the addressable memories. Each one of the addressable memories includes: a control logic for receiving the operation request and addresses of the first and second data from one of the controllers; a random access memory; and a buffer memory coupled between the bus and a random access memory. The buffer memory has a write buffer memory adapted to store the first data in response to the control logic and a read buffer memory adapted to store the second data. The second data is read from the random access memory in response to the control logic. The buffer memory includes an operation selection section having a plurality of operation units configured to perform a different predetermined operation on the first and second data fed to a pair of input ports thereof. One input port is fed by an output of the write buffer memory and the other input port is fed by an output of the read buffer memory. The operation selection section also includes a selector, fed by outputs of the plurality of logic sections, for coupling one of the operation unit outputs to the random access memory selectively in accordance with the operation requested by the controller.
摘要翻译：一种具有用于存储全局变量的多个可寻址存储器的数据存储系统。多个控制器中的每一个适于对存储在可寻址存储器中的第一和第二数据请求操作。每个可寻址存储器包括：用于从控制器之一接收操作请求和第一和第二数据的地址的控制逻辑; 随机存取存储器以及耦合在总线和随机存取存储器之间的缓冲存储器。缓冲存储器具有适于存储响应于控制逻辑的第一数据的写缓冲存储器和适于存储第二数据的读缓冲存储器。响应于控制逻辑从随机存取存储器读取第二数据。缓冲存储器包括具有多个操作单元的操作选择部分，其被配置为对被馈送到其一对输入端口的第一和第二数据执行不同的预定操作。一个输入端口由写缓冲存储器的输出馈送，另一个输入端口由读缓冲存储器的输出馈送。操作选择部分还包括由多个逻辑部分的输出馈送的选择器，用于根据控制器请求的操作有选择地将一个操作单元输出耦合到随机存取存储器。

46. 发明授权

US06195770B1 Data storage system 失效
标题翻译：数据存储系统
公开(公告)号：US06195770B1
公开(公告)日：2001-02-27
申请号：US09052266
申请日：1998-03-31
申请人： John K. Walton
发明人： John K. Walton
IPC分类号： G06F1122
CPC分类号： G06F11/0772 , G06F11/0727 , G06F11/0745
摘要： A data storage system wherein a host computer section having host computer processors for processing data is coupled to a bank of disk drives through an interface. The interface includes a plurality of controllers coupled to a bus. Each one of the controllers is adapted to request a data transfer between the bus and an addressed one of the addressable memories. Each such request is transmitted to the addressed one of the memories in bursts. Each one of the bursts in a request has a tag unique to such request. The bursts from one of the requesting controllers to the one of the addressed memories addressed by such one of the controllers are interleaved with bursts of requests from another one of the requesting controllers to the same or another one of the addressed memories addressed by said another one of the controllers. Each one of the addressable memories has a control logic coupled to the bus for receiving the request from the one of the controllers addressing such one of the addressable memories. The control logic has a storage section. The addressable memory includes a random access memory coupled to the bus through the control logic. An error detector is included in the addressable memory for detecting an error in the addressable memory when transferring data between the bus and the random access memory. The control logic stores in the storage section a cumulative error message produced in response to the error detector processing each one of the bursts of requests and for reports the cumulative error to the one of the controllers making such request.
摘要翻译：一种数据存储系统，其中具有用于处理数据的主计算机处理器的主计算机部分通过接口耦合到一组磁盘驱动器。接口包括耦合到总线的多个控制器。每个控制器适于请求在总线和寻址的可寻址存储器之间的数据传输。每个这样的请求以突发方式发送到寻址的一个存储器。请求中的每一个突发都具有这样的请求唯一的标签。从这些控制器之一寻址的请求控制器之一的寻址存储器之一的脉冲串与来自另一个请求控制器的请求脉冲串交织到由另一个寻址的寻址的存储器寻址的同一个或另一个的控制器。可寻址存储器中的每一个具有耦合到总线的控制逻辑，用于从寻址这样一个可寻址存储器的控制器之一接收请求。控制逻辑具有存储部分。可寻址存储器包括通过控制逻辑耦合到总线的随机存取存储器。在可寻址存储器中包括错误检测器，用于在总线和随机存取存储器之间传送数据时检测可寻址存储器中的错误。控制逻辑在存储部分中存储响应于错误检测器处理每个请求突发而产生的累积错误消息，并将累积错误报告给进行这种请求的控制器之一。

47. 发明授权

US6145042A Timing protocol for a data storage system 失效
标题翻译：数据存储系统的时序协议
公开(公告)号：US6145042A
公开(公告)日：2000-11-07
申请号：US996809
申请日：1997-12-23
申请人： John K. Walton
发明人： John K. Walton
IPC分类号： G06F3/06 , G06F12/08 , G06F12/00
CPC分类号： G06F3/0611 , G06F3/0659 , G06F3/0689 , G06F12/0866
摘要： A data storage system wherein a main frame computer section having main frame processors for processing data is coupled to a bank of disk drives through an interface. The interface includes a bus having: an bus-select/address/command portion; bus-grant/data/clock-pulse portion; a bus queue portion; and an ending-status portion. A plurality of addressable memories is coupled to the bus. A plurality of controllers is coupled to the bus. Each one thereof being adapted: to assert on the bus-select/command/address portion of the bus, during a controller initiated bus select assert interval, a command. The addressed memory is adapted to produce on the queue portion of the bus a queue signal a predetermined time after a controller initiated bus select assert interval. The queue signal terminates the bus select interval. Another one of the controllers is adapted to provide on the bus-select/address/command portion of the bus another address and command after the queue signal terminates the bus select assert interval. The memory is adapted to write, in response to the write operation request by the controller during the bus grant interval, the data on the bus-grant/data/clock-pulse portion of the bus into the addressed memory in response the bus write clock pulses produced by the controller on the bus-grant/data/clock-pulse portion of the bus. The memory is adapted to remove the bus grant signal upon completion of the write operation requested by the controller terminating the bus grant interval and to produce an ending-status signal and ending-status data on the ending-status bus upon the addressed memory's completion of the write operation requested by the controller.
摘要翻译：一种数据存储系统，其中具有用于处理数据的主帧处理器的主帧计算机部分通过接口耦合到一组磁盘驱动器。该接口包括总线，其具有：总线选择/地址/命令部分; 总线授权/数据/时钟脉冲部分; 总线队列部分; 和结束状态部分。多个可寻址存储器耦合到总线。多个控制器耦合到总线。其中每一个适用于：在控制器发起的总线选择断言间隔期间，在总线的总线选择/命令/地址部分上断言一个命令。所寻址的存储器适于在控制器发起的总线选择断言间隔之后的预定时间内在总线的队列部分上产生队列信号。队列信号终止总线选择间隔。另一个控制器适于在队列信号终止总线选择断言间隔之后，在总线上的总线选择/地址/命令部分提供另一地址和命令。存储器适于响应于控制器在总线授权间隔期间的写入操作请求，将母线的总线授权/数据/时钟脉冲部分上的数据写入寻址的存储器中，以响应总线写入时钟总线授权/数据/时钟脉冲部分由控制器产生的脉冲。存储器适于在终止总线许可间隔的控制器请求的写入操作完成时去除总线许可信号，并且在寻址的存储器完成时产生结束状态信号和结束状态数据控制器要求的写操作。

48. 发明授权

US5953265A Memory having error detection and correction 失效
标题翻译：具有错误检测和校正的存储器
公开(公告)号：US5953265A
公开(公告)日：1999-09-14
申请号：US941509
申请日：1997-09-29
申请人： John K. Walton , Christopher S. Maclellan
发明人： John K. Walton , Christopher S. Maclellan
IPC分类号： G06F11/10 , G11C7/00
CPC分类号： G06F11/1008 , G06F11/1028
摘要： A memory system having: a plurality of memory packages for storing words, each one of the packages being adapted to store a plurality of different bits of the word; and an error detection and correction system adapted to detect an error produced in any one of the packages in storing the digital word. With such an arrangement, an error produced by a defect in one of plurality of memory packages, each adapted to store more than one bit of a digital word, may be corrected without requiring changes to other EDACs used in a system employing such memory system. The memory system has a buffer for storing a digital word having N bits of data and M redundant bits for error detection and correction. An error correction code generator is provided for converting the digital word into a second digital word having N bits of data and P redundant bits for error detection and correction. A memory is used for storing the N+P digital word. A error correction code detector corrects an error the data read from the memory.
摘要翻译：一种存储器系统，具有：用于存储字的多个存储器包，所述包中的每一个适于存储所述字的多个不同位; 以及错误检测和校正系统，其适于检测在存储数字字中的任何一个包中产生的错误。通过这样的布置，可以在不需要改变使用这种存储器系统的系统中使用的其它EDAC的情况下校正由适用于存储多于一位数字字的多个存储器包之一中的缺陷产生的错误。存储器系统具有用于存储具有N位数据的数字字和用于错误检测和校正的M个冗余位的缓冲器。提供了一种纠错码发生器，用于将数字字转换为具有N位数据的第二数字字和用于错误检测和校正的P个冗余位。存储器用于存储N + P数字字。纠错码检测器校正从存储器读取的数据的错误。

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