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41. 发明授权

US5883850A Programmable logic array integrated circuits 失效
公开(公告)号：US5883850A
公开(公告)日：1999-03-16
申请号：US664919
申请日：1996-06-18
申请人： Fung Fung Lee , Richard G. Cliff , L. Todd Cope , Cameron R. McClintock , William Leong , James A. Watson , Joseph Huang , Bahram Ahanin
发明人： Fung Fung Lee , Richard G. Cliff , L. Todd Cope , Cameron R. McClintock , William Leong , James A. Watson , Joseph Huang , Bahram Ahanin
IPC分类号： G11C8/12 , H03K19/173 , H03K19/177 , G11C13/00
CPC分类号： H03K19/17736 , G11C8/12 , H03K19/1737 , H03K19/17704 , H03K19/17728
摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

42. 发明授权

US5828229A Programmable logic array integrated circuits 失效
标题翻译：可编程逻辑阵列集成电路
公开(公告)号：US5828229A
公开(公告)日：1998-10-27
申请号：US847004
申请日：1997-05-01
申请人： Richard G. Cliff , L. Todd Cope , Cameron McClintock , William Leong , James Allen Watson , Joseph Huang , Bahram Ahanin , Chiakang Sung , Wanli Chang
发明人： Richard G. Cliff , L. Todd Cope , Cameron McClintock , William Leong , James Allen Watson , Joseph Huang , Bahram Ahanin , Chiakang Sung , Wanli Chang
IPC分类号： G01R31/3185 , G11C8/12 , G11C8/16 , G11C29/32 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1737 , G11C29/32 , G11C8/12 , G11C8/16 , H03K19/17704 , H03K19/17728 , H03K19/1776 , H03K19/17764 , G01R31/318516
摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors. A relatively large block of random access memory ("RAM") may be provided on the device for use as read-only memory ("ROM") or RAM during operation of the device to perform logic. The RAM block is connected in the circuitry of the device so that it can be programmed and verified compatibly with other memory on the device. Thereafter the circuitry of the RAM block allows it to be switched over to operation as RAM or ROM during logic operation of the device.
摘要翻译：可编程逻辑阵列集成电路具有多个可编程逻辑模块，它们被组合在多个逻辑阵列块（“LAB”）中。 LAB以二维阵列布置在电路上。提供一个导线网络，用于将任何逻辑模块与任何其他逻辑模块相互连接。此外，相邻或附近的逻辑模块可以彼此连接，用于在逻辑模块之间提供进位链和/或用于将两个或多个模块连接在一起以提供更复杂的逻辑功能而不必利用一般互连的特殊目的网络。提供了所谓的快速或通用导体的另一网络，用于在整个电路中分布广泛使用的逻辑信号，例如时钟和清除信号。多路复用器可以以各种方式用于减少信号导体之间所需的可编程互连数量。随机存取存储器（“RAM”）相对较大的块可以在设备的操作期间被提供在设备上用作只读存储器（“ROM”）或RAM，以执行逻辑。 RAM块连接在设备的电路中，使其可以与设备上的其他存储器进行编程和验证。此后，RAM块的电路允许在设备的逻辑运行期间将其切换到作为RAM或ROM的操作。

43. 发明授权

US5764583A Programmable logic array integrated circuits 失效
公开(公告)号：US5764583A
公开(公告)日：1998-06-09
申请号：US852015
申请日：1997-05-06
申请人： Richard G. Cliff , L. Todd Cope , Cameron R. McClintock , William Leong , James A. Watson , Joseph Huang , Bahram Ahanin
发明人： Richard G. Cliff , L. Todd Cope , Cameron R. McClintock , William Leong , James A. Watson , Joseph Huang , Bahram Ahanin
IPC分类号： G01R31/3185 , G11C8/12 , H03K19/094 , H03K19/173 , H03K19/177 , G11C13/00
CPC分类号： H03K19/09429 , G11C8/12 , H03K19/1737 , H03K19/17704 , H03K19/17728 , H03K19/17736 , H03K19/1774 , H03K19/1776 , H03K19/1778 , H03K19/17792 , G01R31/318516
摘要： A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

44. 发明授权

US5633830A Random access memory block circuitry for programmable logic array integrated circuit devices 失效
标题翻译：用于可编程逻辑阵列集成电路器件的随机存取存储器块电路
公开(公告)号：US5633830A
公开(公告)日：1997-05-27
申请号：US555106
申请日：1995-11-08
申请人： Chiakang Sung , Wanli Chang , Joseph Huang , Richard G. Cliff
发明人： Chiakang Sung , Wanli Chang , Joseph Huang , Richard G. Cliff
IPC分类号： G01R31/3185 , G11C8/12 , G11C8/16 , G11C29/32 , H03K19/173 , H03K19/177 , G11C7/00
CPC分类号： H03K19/1737 , G11C29/32 , G11C8/12 , G11C8/16 , H03K19/17704 , H03K19/17728 , H03K19/1776 , H03K19/17764 , G01R31/318516
摘要： A relatively large block of random access memory ("RAM") may be provided on a programmable logic array integrated circuit device for use as read-only memory ("ROM") or RAM during operation of the device to perform logic. The RAM block is connected in the circuitry of the device so that it can be programmed and verified compatibly with other memory on the device. Thereafter the circuitry of the RAM block allows it to be switched over to operation as RAM or ROM during logic operation of the device.
摘要翻译：可以在可编程逻辑阵列集成电路装置上提供相对较大的随机存取存储器块（“RAM”），用于在设备操作期间用作只读存储器（“ROM”）或RAM以执行逻辑。 RAM块连接在设备的电路中，使其可以与设备上的其他存储器进行编程和验证。此后，RAM块的电路允许在设备的逻辑运行期间将其切换到作为RAM或ROM的操作。

45. 发明授权

US5555214A Apparatus for serial reading and writing of random access memory arrays 失效
标题翻译：用于串行读取和写入随机存取存储器阵列的装置
公开(公告)号：US5555214A
公开(公告)日：1996-09-10
申请号：US555110
申请日：1995-11-08
申请人： Chiakang Sung , Wanli Chang , Joseph Huang
发明人： Chiakang Sung , Wanli Chang , Joseph Huang
IPC分类号： G11C7/10 , G11C7/22 , G11C7/00
CPC分类号： G11C7/103 , G11C7/22
摘要： A method of serially reading and writing random access memory arrays is provided. Although the read/write inputs continually change as programming data are clocked into the input buffers, a read/write control circuit prevents the constantly changing read/write inputs from causing undesired reading and writing.
摘要翻译：提供了串行读取和写入随机存取存储器阵列的方法。尽管读/写输入随着编程数据被输入到输入缓冲器而不断变化，但读/写控制电路可以防止不断变化的读/写输入引起不期望的读和写。

46. 发明授权

US08787097B1 Circuit design technique for DQS enable/disable calibration 有权
标题翻译： DQS的电路设计技术启用/禁用校准
公开(公告)号：US08787097B1
公开(公告)日：2014-07-22
申请号：US13250155
申请日：2011-09-30
申请人： Yan Chong , Joseph Huang , Sean Shau-Tu Lu , Pradeep Nagarajan , Chiakang Sung
发明人： Yan Chong , Joseph Huang , Sean Shau-Tu Lu , Pradeep Nagarajan , Chiakang Sung
IPC分类号： G11C7/00
CPC分类号： G06F17/5031 , G06F2217/84 , G11C7/1066
摘要： Systems and methods are disclosed for calibrating a Data Strobe (DQS) enable/disable signal and for tracking the timing of the DQS enable/disable signal with respect to changes in voltage and temperature (VT) in order to improve the timing margin of the DQS enable/disable signal in programmable devices using Double Data Rate (DDR) memory. In an exemplary embodiment, the system includes a gating circuit, a sampling circuit, and a delay chain tracking circuit. The gating circuit receives a DQS enable signal and a input DQS signal, calibrates the DQS enable signal based on an amount of delay, and outputs the calibrated DQS signal. The sampling circuit provides the amount of delay to the gating circuit based on a sampling clock. The delay chain tracking circuit maintains the timing of the calibrated DQS enable signal over a plurality of clock cycles based on the sampling clock and a leveling clock.
摘要翻译：公开了用于校准数据选通（DQS）使能/禁止信号的系统和方法，并且用于跟踪DQS使能/禁止信号相对于电压和温度（VT）的变化的定时，以便改善DQS的定时裕度使用双倍数据速率（DDR）存储器在可编程器件中启用/禁用信号。在示例性实施例中，该系统包括门控电路，采样电路和延迟链跟踪电路。门控电路接收DQS使能信号和输入DQS信号，根据延迟量校准DQS使能信号，并输出校准的DQS信号。采样电路基于采样时钟向门控电路提供延迟量。延迟链跟踪电路基于采样时钟和调平时钟在多个时钟周期上维持校准的DQS使能信号的定时。

47. 发明授权

US08723575B1 Configurable delay circuitry with compensated delay 有权
标题翻译：具有补偿延迟的可配置延迟电路
公开(公告)号：US08723575B1
公开(公告)日：2014-05-13
申请号：US13554293
申请日：2012-07-20
申请人： Ee Mei Ooi , Kin Hong Au , Ket Chiew Sia , Yan Chong , Joseph Huang
发明人： Ee Mei Ooi , Kin Hong Au , Ket Chiew Sia , Yan Chong , Joseph Huang
IPC分类号： H03H11/26
CPC分类号： H03H11/265
摘要： An integrated circuit may include a delay circuit that receives an input signal at a first logic level and produces a delayed output signal at a second logic level at an output terminal. The integrated circuit may include a preset circuit coupled to the delay circuit. The preset circuit may receive the input signal and pre-drive the delayed output signal to an intermediate logic level that lies between the first and second logic levels.
摘要翻译：集成电路可以包括延迟电路，其以第一逻辑电平接收输入信号，并在输出端产生处于第二逻辑电平的延迟的输出信号。集成电路可以包括耦合到延迟电路的预设电路。预置电路可以接收输入信号并将延迟的输出信号预驱动到位于第一和第二逻辑电平之间的中间逻辑电平。

48. 发明授权

US08390315B1 Configurable input-output (I/O) circuitry with pre-emphasis circuitry 有权
标题翻译：具有预加重电路的可组态输入输出（I / O）电路
公开(公告)号：US08390315B1
公开(公告)日：2013-03-05
申请号：US13354780
申请日：2012-01-20
申请人： Xiaobao Wang , Chiakang Sung , Joseph Huang , Khai Nguyen
发明人： Xiaobao Wang , Chiakang Sung , Joseph Huang , Khai Nguyen
IPC分类号： H03K19/013 , H03K17/16
CPC分类号： H03K19/01721 , H03K19/018571
摘要： Circuits and techniques for operating an integrated circuit (IC) with a configurable input-output circuit are disclosed. A disclosed circuit includes a single-ended input-output buffer coupled to an output terminal. The single-ended input-output buffer is operable to transmit an input signal to the output terminal as an output signal. A pre-emphasis circuit that is operable to sharpen a first edge and a second edge of the output signal is coupled between the single-ended input-output buffer and the output terminal. The first edge of the output signal is sharpened when the input signal switches from a first logic level to a second logic level while the second edge of the output signal is sharpened when the input signal switches from the second logic level to the first logic level.
摘要翻译：公开了具有可配置的输入 - 输出电路来操作集成电路（IC）的电路和技术。所公开的电路包括耦合到输出端子的单端输入 - 输出缓冲器。单端输入 - 输出缓冲器可用于将输入信号作为输出信号发送到输出端。用于锐化输出信号的第一边缘和第二边缘的预加重电路耦合在单端输入 - 输出缓冲器和输出端子之间。当输入信号从第一逻辑电平切换到第二逻辑电平时，输出信号的第一边缘被锐化，而当输入信号从第二逻辑电平切换到第一逻辑电平时，输出信号的第二边沿被锐化。

49. 发明申请

US20130044423A1 MEMORY STICK HAVING A LOCK DEVICE 有权
标题翻译：具有锁定装置的记忆棒
公开(公告)号：US20130044423A1
公开(公告)日：2013-02-21
申请号：US13213045
申请日：2011-08-18
申请人： Joseph Huang
发明人： Joseph Huang
IPC分类号： H05K7/00
CPC分类号： H05K5/0278
摘要： A memory stick having a lock device includes a metal housing, a PC board, a tray carrying the PC board, lock body, a lock body having a positioning block press-fitted into a top opening of the metal housing and a locating block engaged into a top notch of the metal housing and adapted for accommodating an upper part of the tray and a part of an IC package circuit of the PC board for enabling the USB interface circuit to be suspending in a bottom opening of the metal housing, and a locking mechanism for enabling the memory stick to be locked to an external object.
摘要翻译：具有锁定装置的记忆棒包括金属壳体，PC板，承载PC板的托盘，锁体，具有压配合到金属壳体的顶部开口中的定位块的锁体和与金属壳体接合的定位块金属外壳的顶部槽口，并且适于容纳托盘的上部和PC板的IC封装电路的一部分，以使USB接口电路能够悬挂在金属外壳的底部开口中，并且锁定使记忆棒被锁定到外部对象的机构。

50. 发明授权

US08179669B2 Retractable USB memory stick 有权
标题翻译：伸缩式USB记忆棒
公开(公告)号：US08179669B2
公开(公告)日：2012-05-15
申请号：US12793089
申请日：2010-06-03
申请人： Joseph Huang
发明人： Joseph Huang
IPC分类号： G06F1/16 , H05K5/00 , H05K7/00
CPC分类号： H05K5/0278 , G06K19/077 , G06K19/07732
摘要： A retractable USB memory stick includes a metal casing formed of a seamless flat tube having opposing front opening and rear opening, a sliding slot located on one peripheral wall thereof, and first and second locating holes located on the sliding slot, a PC board having a front USB interface circuit and a rear memory IC package, and an insulation PC board holder holding the PC board and slidably mounted in the metal casing. The insulation PC board holder has a spring strip bridged on the outside wall thereof, a sliding block located on the spring strip and forced by the spring power of the spring strip into the sliding slot of the metal casing, and a retaining block protruded from the sliding block for selectively engaging the first locating hole or second locating hole of the metal casing to lock the insulation PC board holder to the metal casing in the extended position and received position.
摘要翻译：可伸缩的USB记忆棒包括由具有相对的前开口和后开口的无缝扁平管形成的金属外壳，位于其一个外围壁上的滑动槽和位于滑槽上的第一和第二定位孔，前置USB接口电路和后置存储器IC封装，以及保持PC板并可滑动地安装在金属外壳中的绝缘PC板支架。绝缘PC板支架具有桥接在其外壁上的弹簧条，位于弹簧条上并被弹簧带的弹簧力推动到金属外壳的滑动槽中的滑块，以及从金属外壳突出的保持块滑动块，用于选择性地接合金属壳体的第一定位孔或第二定位孔，以将绝缘PC板保持器锁定在延伸位置的金属壳体和接收位置。

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