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41. 发明授权

US08044510B2 Product and method for integration of deep trench mesh and structures under a bond pad 有权
标题翻译：深沟槽网格和结合垫下结构的整合的产品和方法
公开(公告)号：US08044510B2
公开(公告)日：2011-10-25
申请号：US12256089
申请日：2008-10-22
申请人： Ephrem G. Gebreselasie , William T. Motsiff , Wolfgang Sauter , Steven H. Voldman
发明人： Ephrem G. Gebreselasie , William T. Motsiff , Wolfgang Sauter , Steven H. Voldman
IPC分类号： H01L23/48
CPC分类号： H01L27/0207 , H01L21/76224 , H01L21/823481 , H01L21/8249 , H01L27/08 , H01L2924/0002 , H01L2924/00
摘要： A structure includes a substrate. A trench structure is arranged within the substrate. A film is placed under an interlevel dielectric pad and between portions of the trench structure.
摘要翻译：一种结构包括基底。沟槽结构布置在衬底内。将薄膜放置在层间介质垫之下和沟槽结构的部分之间。

42. 发明授权

US08015538B2 Design structure with a deep sub-collector, a reach-through structure and trench isolation 有权
标题翻译：具有深子集电极的设计结构，通孔结构和沟槽隔离
公开(公告)号：US08015538B2
公开(公告)日：2011-09-06
申请号：US11941104
申请日：2007-11-16
申请人： Douglas D Coolbaugh , Xuefeng Liu , Robert M. Rassel , David C. Sheridan , Steven H. Voldman
发明人： Douglas D Coolbaugh , Xuefeng Liu , Robert M. Rassel , David C. Sheridan , Steven H. Voldman
IPC分类号： G06F17/50 , G06F11/22 , G06F9/455 , H01L29/00 , H01L21/8238 , H01L21/20
CPC分类号： H01L29/0821 , H01L29/66272
摘要： The invention relates to noise isolation in semiconductor devices, and a design structure on which a subject circuit resides. A design structure is embodied in a machine readable medium used in a design process. The design structure includes a deep sub-collector located in a first epitaxial layer, and a doped region located in a second epitaxial layer, which is above the first epitaxial layer. The design structure further includes a reach-through structure penetrating from a surface of the device through the first and second epitaxial layers to the deep sub-collector, and a trench isolation structure penetrating from a surface of the device and surrounding the doped region.
摘要翻译：本发明涉及半导体器件中的噪声隔离以及被摄体电路所在的设计结构。设计结构体现在在设计过程中使用的机器可读介质中。该设计结构包括位于第一外延层中的深子集电极和位于第一外延层之上的第二外延层中的掺杂区域。该设计结构进一步包括从装置的表面穿过第一外延层和第二外延层到达深亚集电体的通孔结构，以及从该器件的表面穿透且围绕掺杂区域的沟槽隔离结构。

43. 发明授权

US07886240B2 Modifying layout of IC based on function of interconnect and related circuit and design structure 有权
标题翻译：基于互连功能和相关电路以及设计结构修改IC布局
公开(公告)号：US07886240B2
公开(公告)日：2011-02-08
申请号：US12021333
申请日：2008-01-29
申请人： James W. Adkisson , Natalie B. Feilchenfeld , Jeffrey P. Gambino , Howard S. Landis , Benjamin T. Voegeli , Steven H. Voldman , Michael J. Zierak
发明人： James W. Adkisson , Natalie B. Feilchenfeld , Jeffrey P. Gambino , Howard S. Landis , Benjamin T. Voegeli , Steven H. Voldman , Michael J. Zierak
IPC分类号： G06F17/50 , G06F7/38 , H01L25/00 , H03K19/00
CPC分类号： G06F17/5081
摘要： Modifying a layout of an integrated circuit (IC) based on a function of an interconnect therein and a related circuit and design structure are disclosed. In one embodiment, a method includes identifying a function of an interconnect in the layout from data of the layout embodied in a computer readable medium; and modifying the layout to form another layout that accommodates the function of the interconnect. A design structure embodied in a machine readable medium used in a design process, according to one embodiment, may include a circuit including a high voltage interconnect positioned in a dielectric layer, the high voltage interconnect positioned such that no fill is above or below the high voltage interconnect.
摘要翻译：公开了基于互连功能的集成电路（IC）的布局以及相关的电路和设计结构。在一个实施例中，一种方法包括根据体现在计算机可读介质中的布局的数据来识别布局中的互连的功能; 并修改布局以形成适应互连功能的另一布局。根据一个实施例，体现在设计过程中使用的机器可读介质中的设计结构可以包括电路，该电路包括定位在电介质层中的高电压互连，所述高压互连被定位成使得没有填充物高于或低于高电压互连。

44. 发明授权

US07855104B2 Structure and method for latchup suppression 有权
标题翻译：闭锁抑制的结构和方法
公开(公告)号：US07855104B2
公开(公告)日：2010-12-21
申请号：US11776738
申请日：2007-07-12
申请人： Steven H. Voldman
发明人： Steven H. Voldman
IPC分类号： H01L21/332
CPC分类号： H01L21/8249 , H01L27/0623 , H01L27/0921 , H01L27/0928
摘要： A method and structure for an integrated circuit comprising a substrate of a first polarity, a merged triple well region of a second polarity and a doped region of the second polarity abutting the well region. The doped region is adapted to suppress latch-up in the integrated circuit. The doped region is placed under semiconductor devices of the first polarity and under the well region contact region. Additionally, the structure may further include a deep trench (DT) structure and trench isolation (TI) structure to further improve latchup robustness.
摘要翻译：一种用于集成电路的方法和结构，该集成电路包括第一极性的衬底，第二极性的合并三阱区域和第二极性的掺杂区域邻接阱区域。掺杂区域适于抑制集成电路中的闩锁。将掺杂区域放置在第一极性的半导体器件之下并且位于阱区域接触区域下方。另外，该结构还可以包括深沟槽（DT）结构和沟槽隔离（TI）结构，以进一步提高闭锁鲁棒性。

45. 发明授权

US07821099B2 Structure for low capacitance ESD robust diodes 有权
标题翻译：低容量ESD稳健二极管的结构
公开(公告)号：US07821099B2
公开(公告)日：2010-10-26
申请号：US12118875
申请日：2008-05-12
申请人： Steven H. Voldman
发明人： Steven H. Voldman
IPC分类号： H01L29/861
CPC分类号： H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： A diode having a capacitance below 0.1 pF and a breakdown voltage of at least 500V. The diode has an anode of a first conductivity type and a cathode of a second conductivity type disposed below the anode. At least one of the cathode and anode have multiple, vertically abutting diffusion regions. The cathode and anode are disposed between and bounded by adjacent isolation regions.
摘要翻译：具有低于0.1pF的电容和至少500V的击穿电压的二极管。二极管具有第一导电类型的阳极和布置在阳极下方的第二导电类型的阴极。阴极和阳极中的至少一个具有多个垂直邻接的扩散区域。阴极和阳极设置在相邻隔离区之间并由其限定。

46. 发明申请

US20100244112A1 INTEGRATED CIRCUIT STRUCTURES WITH SILICON GERMANIUM FILM INCORPORATED AS LOCAL INTERCONNECT AND/OR CONTACT 有权
标题翻译：集成电路结构与硅锗电容器作为本地互连和/或联系
公开(公告)号：US20100244112A1
公开(公告)日：2010-09-30
申请号：US12815622
申请日：2010-06-15
申请人： Steven H. Voldman
发明人： Steven H. Voldman
IPC分类号： H01L27/108 , H01L29/92
CPC分类号： H01L27/1104 , H01L21/28525 , H01L21/76895 , H01L27/10867 , H01L27/11 , H01L29/66181
摘要： Disclosed are integrated circuit structures each having a silicon germanium film incorporated as a local interconnect and/or an electrical contact. These integrated circuit structures provide improved local interconnects between devices and/or increased capacitance to devices without significantly increasing structure surface area or power requirements. Specifically, disclosed are integrated circuit structures that incorporate a silicon germanium film as one or more of the following features: as a local interconnect between devices; as an electrical contact to a device (e.g., a deep trench capacitor, a source/drain region of a transistor, etc.); as both an electrical contact to a deep trench capacitor and a local interconnect between the deep trench capacitor and another device; and as both an electrical contact to a deep trench capacitor and as a local interconnect between the deep trench capacitor and other devices.
摘要翻译：公开了各自具有并入作为局部互连和/或电接触的硅锗膜的集成电路结构。这些集成电路结构在器件之间提供改进的局部互连和/或增加对器件的电容，而不显着增加结构表面面积或功率要求。具体地，公开了将硅锗膜作为一个或多个以下特征的集成电路结构：作为器件之间的局部互连; 作为与器件（例如，深沟槽电容器，晶体管的源极/漏极区域等）的电接触; 作为与深沟槽电容器的电接触和深沟槽电容器与另一器件之间的局部互连的两者; 并且作为与深沟槽电容器的电接触以及作为深沟槽电容器和其他器件之间的局部互连的两者。

47. 发明申请

US20100175035A1 INTEGRATED CIRCUIT STRUCTURE INCORPORATING AN INDUCTOR, AN ASSOCIATED DESIGN METHOD AND AN ASSOCIATED DESIGN SYSTEM 失效
标题翻译：集成电路结构，电感设计，相关设计方法和相关设计系统
公开(公告)号：US20100175035A1
公开(公告)日：2010-07-08
申请号：US12720728
申请日：2010-03-10
申请人： Zhong-Xiang He , Robert M. Rassel , Steven H. Voldman
发明人： Zhong-Xiang He , Robert M. Rassel , Steven H. Voldman
IPC分类号： G06F17/50
CPC分类号： G06F17/5063 , H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Disclosed are embodiments of a circuit (e.g., an electrostatic discharge (ESD) circuit), a design methodology and a design system. In the circuit, an ESD device is wired to a first metal level (e.g., M1). An inductor is formed in a second metal level (e.g., M5) above the first metal level and is aligned over and electrically connected in parallel to the ESD device by a single vertical via stack. The inductor is configured to nullify, for a given application frequency, the capacitance value of the ESD device. The quality factor of the inductor is optimized by providing, on a third metal level (e.g., M3) between the second metal level and the first metal level, a shield to minimize inductive coupling. An opening in the shield allows the via stack to pass through, trading off Q factor reduction for size-scaling and ESD robustness improvements.
摘要翻译：公开了电路（例如，静电放电（ESD）电路）的实施例，设计方法和设计系统。在该电路中，ESD器件被连接到第一金属级（例如，M1）。电感器形成在第一金属层上方的第二金属层（例如M5）中，并且通过单个垂直通孔叠层对准并与ESD器件电连接。电感器被配置为对于给定的应用频率，使ESD器件的电容值无效。通过在第二金属层与第一金属层之间的第三金属层（例如M3）上设置用于最小化电感耦合的屏蔽来优化电感器的品质因数。屏蔽开口允许通孔堆叠通过，减小尺寸缩放和ESD稳健性改进的Q因子。

48. 发明授权

US07750408B2 Integrated circuit structure incorporating an inductor, a conductive sheet and a protection circuit 失效
标题翻译：集成电路结构，包括电感器，导电片和保护电路
公开(公告)号：US07750408B2
公开(公告)日：2010-07-06
申请号：US11692948
申请日：2007-03-29
申请人： Zhong-Xiang He , Robert M. Rassel , Steven H. Voldman
发明人： Zhong-Xiang He , Robert M. Rassel , Steven H. Voldman
IPC分类号： H01L23/62
CPC分类号： G06F17/5063 , H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Disclosed are embodiments of a circuit (e.g., an electrostatic discharge (ESD) circuit), a design methodology and a design system. In the circuit, an ESD device is wired to a first metal level (e.g., M1). An inductor is formed in a second metal level (e.g., M5) above the first metal level and is aligned over and electrically connected in parallel to the ESD device by a single vertical via stack. The inductor is configured to nullify, for a given application frequency, the capacitance value of the ESD device. The quality factor of the inductor is optimized by providing, on a third metal level (e.g., M3) between the second metal level and the first metal level, a shield to minimize inductive coupling. An opening in the shield allows the via stack to pass through, trading off Q factor reduction for size-scaling and ESD robustness improvements.
摘要翻译：公开了电路（例如，静电放电（ESD）电路）的实施例，设计方法和设计系统。在该电路中，ESD器件被连接到第一金属级（例如，M1）。电感器形成在第一金属层上方的第二金属层（例如M5）中，并且通过单个垂直通孔叠层对准并与ESD器件电连接。对于给定的应用频率，电感器被配置为使ESD器件的电容值无效。通过在第二金属层与第一金属层之间的第三金属层（例如M3）上设置用于最小化电感耦合的屏蔽来优化电感器的品质因数。屏蔽开口允许通孔堆叠通过，减小尺寸缩放和ESD稳健性改进的Q因子。

49. 发明申请

US20100032767A1 STRUCTURE AND METHOD OF LATCHUP ROBUSTNESS WITH PLACEMENT OF THROUGH WAFER VIA WITHIN CMOS CIRCUITRY 有权
标题翻译：通过在CMOS电路中通过WAFER放置的锁定稳定性的结构和方法
公开(公告)号：US20100032767A1
公开(公告)日：2010-02-11
申请号：US12186802
申请日：2008-08-06
申请人： Phillip F. Chapman , David S. Collins , Steven H. Voldman
发明人： Phillip F. Chapman , David S. Collins , Steven H. Voldman
IPC分类号： H01L21/762 , H01L27/092
CPC分类号： H01L27/0921 , H01L21/743 , H01L21/76224 , H01L21/76898 , H01L21/823871 , H01L21/823878 , H01L21/823892 , H01L23/481 , H01L27/092 , H01L29/0649 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor structure includes: forming a trench in a back side of a substrate; depositing a dopant on surfaces of the trench; forming a shallow trench isolation (STI) structure in a top side of the substrate opposite the trench; forming a deep well in the substrate; out-diffusing the dopant into the deep well and the substrate; forming an N-well and a P-well in the substrate; and filling the trench with a conductive material.
摘要翻译：一种制造半导体结构的方法包括：在衬底的背面形成沟槽; 在沟槽的表面上沉积掺杂剂; 在与沟槽相对的衬底的顶侧中形成浅沟槽隔离（STI）结构; 在基材中形成深井; 将掺杂剂扩散到深阱和衬底中; 在衬底中形成N阱和P阱; 并用导电材料填充沟槽。

50. 发明申请

US20090261426A1 LATERAL DIFFUSION FIELD EFFECT TRANSISTOR WITH DRAIN REGION SELF-ALIGNED TO GATE ELECTRODE 有权
标题翻译：具有排水区域的侧向扩散场效应晶体管与电极电极对齐
公开(公告)号：US20090261426A1
公开(公告)日：2009-10-22
申请号：US12104643
申请日：2008-04-17
申请人： Natalie B. Feilchenfeld , Jeffrey P. Gambino , Xuefeng Liu , Benjamin T. Voegeli , Steven H. Voldman , Michael J. Zierak
发明人： Natalie B. Feilchenfeld , Jeffrey P. Gambino , Xuefeng Liu , Benjamin T. Voegeli , Steven H. Voldman , Michael J. Zierak
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/26586 , H01L21/26513 , H01L29/1045 , H01L29/6656 , H01L29/66659 , H01L29/7835
摘要： A disposable structure displaced from an edge of a gate electrode and a drain region aligned to the disposable structure is formed. Thus, the drain region is self-aligned to the edge of the gate electrode. The disposable structure may be a disposable spacer, or alternately, the disposable structure may be formed simultaneously with, and comprise the same material as, a gate electrode. After formation of the drain regions, the disposable structure is removed. The self-alignment of the drain region to the edge of the gate electrode provides a substantially constant drift distance that is independent of any overlay variation of lithographic processes.
摘要翻译：形成从栅电极的边缘排列的一次性结构和与一次性结构对准的漏区。因此，漏极区域与栅电极的边缘自对准。一次性结构可以是一次性间隔件，或者替代地，一次性结构可以与栅电极同时形成并且包括与栅电极相同的材料。在形成漏极区域之后，一次性结构被去除。漏极区域到栅电极的边缘的自对准提供了与光刻工艺的任何叠加变化无关的基本恒定的漂移距离。

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