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    • 48. 发明授权
    • Apparatus and method for transmitting/receiving error detection information in a communication system
    • 用于在通信系统中发送/接收错误检测信息的装置和方法
    • US07275198B2
    • 2007-09-25
    • US10742684
    • 2003-12-19
    • Dong-Hee KimHo-Kyu ChoiYoun-Sun KimHwan-Joon Kwon
    • Dong-Hee KimHo-Kyu ChoiYoun-Sun KimHwan-Joon Kwon
    • H03M13/00G01R31/28
    • H04L1/0057H04L1/0045H04L1/0046H04L1/0059H04L1/0061H04L1/0068H04L1/0071H04L1/0072H04L1/08
    • Disclosed is an apparatus for generating an error detection information bit sequence for determining a length of data sequence transmitted in a communication system. The apparatus comprises a plurality of cascaded registers, the number of which is identical to the number of bits in the error detection information bit sequence, and a plurality of adders arranged on paths determined by a predetermined generator polynomial, each of the adders adding a bit sequence received through an input path to a feedback bit sequence. During reception of the control information sequence, an operator generates the feedback bit sequence by sequentially adding bits of the control information sequence to output bits of a final register and provides the generated feedback bit sequence to the adders. After completion of receiving the control information sequence, the operator sequentially adds a preset input bit to output bits of the final register and outputs the addition result as the error detection information bit sequence. An initial value controller provides the registers with a selected initial value separately determined for the data sequences.
    • 公开了一种用于生成用于确定在通信系统中发送的数据序列的长度的错误检测信息比特序列的装置。 该装置包括多个级联寄存器,其数量与错误检测信息位序列中的位数相同,并且多个加法器布置在由预定的生成多项式确定的路径上,每个加法器加一位 通过反馈比特序列的输入路径接收的序列。 在控制信息序列的接收期间,操作者通过顺序地将控制信息序列的比特加到输出终端寄存器的比特来生成反馈比特序列,并将所产生的反馈比特序列提供给加法器。 在完成接收到控制信息序列之后,操作者将预设的输入位顺序地加到最终寄存器的输出位,并输出加法结果作为错误检测信息位序列。 初始值控制器为寄存器提供分别为数据序列确定的所选初始值。