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41. 发明申请

US20090256204A1 SOI TRANSISTOR WITH MERGED LATERAL BIPOLAR TRANSISTOR 失效
标题翻译：具有合并侧向双极晶体管的SOI晶体管
公开(公告)号：US20090256204A1
公开(公告)日：2009-10-15
申请号：US12099879
申请日：2008-04-09
申请人： Jin Cai , Jeffrey B. Johnson , Tak H. Ning , Robert R. Robison
发明人： Jin Cai , Jeffrey B. Johnson , Tak H. Ning , Robert R. Robison
IPC分类号： H01L29/786
CPC分类号： H01L29/78612 , H01L21/84 , H01L27/0722
摘要： A semiconductor-on-insulator transistor device includes a source region, a drain region, a body region, and a source-side lateral bipolar transistor. The source region has a first conductivity type. The body region has a second conductivity type and is positioned between the source region and the drain region. The source-side lateral bipolar transistor includes a base, a collector, and an emitter. A silicide region connects the base to the collector. The emitter is the body region. The collector has the second conductivity type, and the base is the source region and is positioned between the emitter and the collector.
摘要翻译：绝缘体上半导体晶体管器件包括源极区，漏极区，体区和源极横向双极晶体管。源区具有第一导电类型。体区具有第二导电类型并且位于源区和漏区之间。源极横向双极晶体管包括基极，集电极和发射极。硅化物区将基底连接到收集器。发射器是身体区域。集电体具有第二导电类型，基极是源极区，位于发射极和集电极之间。

42. 发明申请

US20090114971A1 CMOS EPROM AND EEPROM DEVICES AND PROGRAMMABLE CMOS INVERTERS 有权
标题翻译： CMOS EPROM和EEPROM器件和可编程CMOS逆变器
公开(公告)号：US20090114971A1
公开(公告)日：2009-05-07
申请号：US11935143
申请日：2007-11-05
申请人： Jin Cai , Tak H. Ning , John M. Safran
发明人： Jin Cai , Tak H. Ning , John M. Safran
IPC分类号： H01L27/092 , H01L27/12
CPC分类号： H01L21/823857 , G11C16/0433 , G11C16/10 , H01L21/823885 , H01L21/84 , H01L27/0922 , H01L27/105 , H01L27/11521 , H01L27/11524 , H01L27/11558 , H01L27/1203 , H01L29/66825 , H01L29/785 , H01L29/7881
摘要： A CMOS EPROM, EEPROM or inverter device includes an nFET device with a thin gate dielectric layer and a pFET device juxtaposed with the nFET device with a thick gate dielectric layer and a floating gate electrode. The thick gate dielectric layer is substantially thicker than the thin gate dielectric layer. A common drain node connected both FET devices has no external connection in the case of a memory device and has an external connection in the case of an inverter. There are external circuit connections to the source regions of both FET devices and to the gate electrode of the nFET device. The pFET and nFET devices can be planar, vertical or FinFET devices.
摘要翻译： CMOS EPROM，EEPROM或逆变器装置包括具有薄栅介质层的nFET器件和与nFET器件并置的pFET器件，其具有厚栅极介电层和浮栅电极。厚栅极电介质层基本上比薄栅极电介质层厚。连接两个FET器件的公共漏极节点在存储器件的情况下没有外部连接，并且在逆变器的情况下具有外部连接。存在与FET器件的源极区域和nFET器件的栅电极的外部电路连接。 pFET和nFET器件可以是平面，垂直或FinFET器件。

43. 发明授权

US06812533B2 SOI based bipolar transistor having a majority carrier accumulation layer as subcollector 有权
标题翻译：具有多数载流子积累层的SOI基双极晶体管作为子集电极
公开(公告)号：US06812533B2
公开(公告)日：2004-11-02
申请号：US10328694
申请日：2002-12-24
申请人： Jin Cai , Tak H. Ning , Qiqing Ouyang
发明人： Jin Cai , Tak H. Ning , Qiqing Ouyang
IPC分类号： H01L2976
CPC分类号： H01L29/66265 , H01L29/0821 , H01L29/7317
摘要： An electronic circuit comprises a bipolar transistor that includes a conductive back electrode, an insulator layer over the conductive back electrode and a semiconductor layer of either an n-type or p-type material over the insulator layer. The semiconductor layer includes a doped region, used as the collector and a heavily doped region, bordering the doped region, used as a reachthrough between the insulator layer and the collector contact electrode. A majority-carrier accumulation layer is induced adjacent to the insulator in the doped region of the collector by the application of a bias voltage to the back electrode.
摘要翻译：电子电路包括双极晶体管，其包括导电背电极，导电背电极之上的绝缘体层以及绝缘体层上的n型或p型材料的半导体层。半导体层包括用作集电极的掺杂区域和与掺杂区域接壤的重掺杂区域，用作绝缘体层和集电极接触电极之间的穿透层。通过向背电极施加偏置电压，在集电极的掺杂区域中与绝缘体相邻地吸引多数载流子堆积层。

44. 发明授权

US08415743B2 ETSOI CMOS with back gates 有权
标题翻译：带后门的ETSOI CMOS
公开(公告)号：US08415743B2
公开(公告)日：2013-04-09
申请号：US13114410
申请日：2011-05-24
申请人： Jin Cai , Robert H Dennard , Ali Khakifirooz
发明人： Jin Cai , Robert H Dennard , Ali Khakifirooz
IPC分类号： H01L27/092
CPC分类号： H01L27/1203
摘要： A structure has a functional region having a first type of conductivity and a top surface. The functional region is connected to a bias contact. The structure further includes an insulating layer; a semiconductor layer and first and second transistor devices having the same type of conductivity disposed upon the semiconductor layer. The structure further includes a first back gate region adjacent to the top surface and underlying one of the transistor devices, the first back gate region having a second type of conductivity; and a second back gate region adjacent to the top surface and underlying the other one of the transistor devices, the second back gate region having the first type of conductivity. The first transistor device has a first characteristic threshold voltage and the second transistor device has a second characteristic threshold voltage that differs from the first characteristic threshold voltage.
摘要翻译：结构具有具有第一类型的导电性的功能区域和顶表面。功能区域连接到偏置触点。该结构还包括绝缘层; 半导体层和具有相同类型导电性的第一和第二晶体管器件设置在半导体层上。所述结构还包括与所述顶表面相邻并且位于所述晶体管器件之一下方的第一后栅极区域，所述第一背栅极区域具有第二类型的导电性; 以及与顶表面相邻并且位于另一个晶体管器件下方的第二背栅极区域，第二背栅极区域具有第一类型的导电性。第一晶体管器件具有第一特征阈值电压，并且第二晶体管器件具有不同于第一特征阈值电压的第二特征阈值电压。

45. 发明申请

US20130005095A1 ETSOI CMOS With Back Gates 有权
标题翻译： ETSOI CMOS后盖
公开(公告)号：US20130005095A1
公开(公告)日：2013-01-03
申请号：US13611656
申请日：2012-09-12
申请人： Jin Cai , Robert H. Dennard , Ali Khakifirooz
发明人： Jin Cai , Robert H. Dennard , Ali Khakifirooz
IPC分类号： H01L21/8238
CPC分类号： H01L27/1203
摘要： A method to fabricate a structure includes providing a silicon-on-insulator wafer, implanting through a semiconductor layer and an insulating layer a functional region having a first type of conductivity to be adjacent to a top surface of the substrate; implanting within the functional region through the semiconductor layer and the insulating layer an electrically floating back gate region having a second type of conductivity; forming isolation regions in the semiconductor layer; forming first and second transistor devices to have the same type of conductivity over the semiconductor layer such that one of the transistor devices overlies the implanted back gate region and the other one of the transistor devices overlies only the underlying top surface of the functional region not overlapped by the implanted back gate region; and providing an electrical contact to the functional region for applying a bias voltage.
摘要翻译：制造结构的方法包括提供绝缘体上硅晶片，通过半导体层和绝缘层注入具有与衬底顶表面相邻的第一导电类型的功能区域; 在功能区域内通过半导体层和绝缘层注入具有第二类导电性的电浮置背栅区; 在半导体层中形成隔离区; 形成第一和第二晶体管器件以在半导体层上具有相同类型的导电性，使得晶体管器件中的一个覆盖在注入的背栅极区域上，另一个晶体管器件仅覆盖不重叠的功能区域的下面的顶部表面通过植入的背栅区; 以及向所述功能区域提供电接触以施加偏置电压。

46. 发明申请

US20120299105A1 ETSOI CMOS with Back Gates 有权
标题翻译：带后盖的ETSOI CMOS
公开(公告)号：US20120299105A1
公开(公告)日：2012-11-29
申请号：US13114410
申请日：2011-05-24
申请人： Jin Cai , Robert H. Dennard , Ali Khakifirooz
发明人： Jin Cai , Robert H. Dennard , Ali Khakifirooz
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/1203
摘要： A structure has a functional region having a first type of conductivity and a top surface. The functional region is connected to a bias contact. The structure further includes an insulating layer; a semiconductor layer and first and second transistor devices having the same type of conductivity disposed upon the semiconductor layer. The structure further includes a first back gate region adjacent to the top surface and underlying one of the transistor devices, the first back gate region having a second type of conductivity; and a second back gate region adjacent to the top surface and underlying the other one of the transistor devices, the second back gate region having the first type of conductivity. The first transistor device has a first characteristic threshold voltage and the second transistor device has a second characteristic threshold voltage that differs from the first characteristic threshold voltage.
摘要翻译：结构具有具有第一类型的导电性的功能区域和顶表面。功能区域连接到偏置触点。该结构还包括绝缘层; 半导体层和具有相同类型导电性的第一和第二晶体管器件设置在半导体层上。所述结构还包括与所述顶表面相邻并且位于所述晶体管器件之一下方的第一后栅极区域，所述第一背栅极区域具有第二类型的导电性; 以及与顶表面相邻并且位于另一个晶体管器件下方的第二背栅极区域，第二背栅极区域具有第一类型的导电性。第一晶体管器件具有第一特征阈值电压，并且第二晶体管器件具有不同于第一特征阈值电压的第二特征阈值电压。

47. 发明授权

US08530287B2 ETSOI CMOS with back gates 有权
标题翻译：带后门的ETSOI CMOS
公开(公告)号：US08530287B2
公开(公告)日：2013-09-10
申请号：US13611656
申请日：2012-09-12
申请人： Jin Cai , Robert H Dennard , Ali Khakifirooz
发明人： Jin Cai , Robert H Dennard , Ali Khakifirooz
IPC分类号： H01L21/84
CPC分类号： H01L27/1203
摘要： A method to fabricate a structure includes providing a silicon-on-insulator wafer, implanting through a semiconductor layer and an insulating layer a functional region having a first type of conductivity to be adjacent to a top surface of the substrate; implanting within the functional region through the semiconductor layer and the insulating layer an electrically floating back gate region having a second type of conductivity; forming isolation regions in the semiconductor layer; forming first and second transistor devices to have the same type of conductivity over the semiconductor layer such that one of the transistor devices overlies the implanted back gate region and the other one of the transistor devices overlies only the underlying top surface of the functional region not overlapped by the implanted back gate region; and providing an electrical contact to the functional region for applying a bias voltage.
摘要翻译：制造结构的方法包括提供绝缘体上硅晶片，通过半导体层和绝缘层注入具有与衬底顶表面相邻的第一导电类型的功能区域; 在功能区域内通过半导体层和绝缘层注入具有第二类导电性的电浮置背栅区; 在半导体层中形成隔离区; 形成第一和第二晶体管器件以在半导体层上具有相同类型的导电性，使得晶体管器件中的一个覆盖在注入的背栅极区域上，另一个晶体管器件仅覆盖不重叠的功能区域的下面的顶部表面通过植入的背栅区; 以及向所述功能区域提供电接触以施加偏置电压。

48. 发明授权

US08852985B2 Graphene pressure sensors 有权
标题翻译：石墨烯压力传感器
公开(公告)号：US08852985B2
公开(公告)日：2014-10-07
申请号：US13600469
申请日：2012-08-31
申请人： Jin Cai , Yanqing Wu , Wenjuan Zhu
发明人： Jin Cai , Yanqing Wu , Wenjuan Zhu
IPC分类号： H01L21/00 , H01L29/02
CPC分类号： H01L29/1606 , G01L9/0042 , G01L9/0051 , H01L27/0802 , H01L29/0649
摘要： Semiconductor nano pressure sensor devices having graphene membrane suspended over open cavities formed in a semiconductor substrate. A suspended graphene membrane serves as an active electro-mechanical membrane for sensing pressure, which can be made very thin, from about one atomic layer to about 10 atomic layers in thickness, to improve the sensitivity and reliability of a semiconductor pressure sensor device.
摘要翻译：半导体纳米压力传感器装置具有悬浮在半导体衬底中形成的开放空腔上的石墨烯膜。悬浮的石墨烯膜用作用于感测压力（其可以制成非常薄）从约一个原子层到约10个原子层的活性电子机械膜，以提高半导体压力传感器装置的灵敏度和可靠性。

49. 发明申请

US20130273682A1 GRAPHENE PRESSURE SENSORS 有权
标题翻译：石墨压力传感器
公开(公告)号：US20130273682A1
公开(公告)日：2013-10-17
申请号：US13600469
申请日：2012-08-31
申请人： Jin Cai , Yanqing Wu , Wenjuan Zhu
发明人： Jin Cai , Yanqing Wu , Wenjuan Zhu
IPC分类号： H01L29/02
CPC分类号： H01L29/1606 , G01L9/0042 , G01L9/0051 , H01L27/0802 , H01L29/0649
摘要： Semiconductor nano pressure sensor devices having graphene membrane suspended over open cavities formed in a semiconductor substrate. A suspended graphene membrane serves as an active electro-mechanical membrane for sensing pressure, which can be made very thin, from about one atomic layer to about 10 atomic layers in thickness, to improve the sensitivity and reliability of a semiconductor pressure sensor device.
摘要翻译：半导体纳米压力传感器装置具有悬浮在半导体衬底中形成的开放空腔上的石墨烯膜。悬浮的石墨烯膜用作用于感测压力（其可以制成非常薄）从约一个原子层到约10个原子层的活性电子机械膜，以提高半导体压力传感器装置的灵敏度和可靠性。

50. 发明申请

US20130270511A1 GRAPHENE PRESSURE SENSORS 有权
标题翻译：石墨压力传感器
公开(公告)号：US20130270511A1
公开(公告)日：2013-10-17
申请号：US13445029
申请日：2012-04-12
申请人： Jin Cai , Yanqing Wu , Wenjuan Zhu
发明人： Jin Cai , Yanqing Wu , Wenjuan Zhu
IPC分类号： H01L29/06 , H01L21/02 , B82Y40/00
CPC分类号： H01L29/1606 , G01L9/0042 , G01L9/0051 , H01L27/0802 , H01L29/0649
摘要： Semiconductor nano pressure sensor devices having graphene membrane suspended over cavities formed in a semiconductor substrate. A suspended graphene membrane serves as an active electro-mechanical membrane for sensing pressure, which can be made very thin, from about one atomic layer to about 10 atomic layers in thickness, to improve the sensitivity and reliability of a semiconductor pressure sensor device.
摘要翻译：半导体纳米压力传感器装置具有悬浮在形成于半导体衬底中的空腔上的石墨烯膜。悬浮的石墨烯膜用作用于感测压力（其可以制成非常薄）从约一个原子层到约10个原子层的活性电子机械膜，以提高半导体压力传感器装置的灵敏度和可靠性。

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