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41. 发明授权

US6081002A Lateral SCR structure for ESD protection in trench isolated technologies 失效
标题翻译：沟槽隔离技术中ESD保护的横向SCR结构
公开(公告)号：US6081002A
公开(公告)日：2000-06-27
申请号：US85818
申请日：1998-05-27
申请人： E. Ajith Amerasekera , Bernhard H. Andresen , Amitava Chatterjee
发明人： E. Ajith Amerasekera , Bernhard H. Andresen , Amitava Chatterjee
IPC分类号： H01L27/02 , H01L29/74
CPC分类号： H01L27/0259 , H01L27/0266
摘要： A protection device for trench isolated technologies. The protection device includes a lateral SCR (100) that incorporates a triggering MOS transistor (120) with a first gate electrode (116) connected to the cathode (112) of the SCR (100). The anode (110) of the lateral SCR (100) is separated from the nearest source/drain region (122) of the triggering MOS transistor (120) by a second gate electrode (132) rather than by trench isolation. By using the second gate electrode (132) for isolation instead of trench isolation, the surface conduction of the lateral SCR (100) in unimpeded.
摘要翻译：一种用于沟槽隔离技术的保护装置。保护装置包括横向SCR（100），其包括触发MOS晶体管（120）和与SCR（100）的阴极（112）连接的第一栅电极（116）。横向SCR（100）的阳极（110）通过第二栅电极（132）而不是通过沟槽隔离与触发MOS晶体管（120）的最近的源极/漏极区域（122）分离。通过使用第二栅电极（132）进行隔离而不是沟槽隔离，横向SCR（100）的表面导通不受阻碍。

42. 发明授权

US6015992A Bistable SCR-like switch for ESD protection of silicon-on-insulator integrated circuits 失效
标题翻译：双稳态SCR型开关，用于绝缘体上硅集成电路的ESD保护
公开(公告)号：US6015992A
公开(公告)日：2000-01-18
申请号：US1058
申请日：1997-12-30
申请人： Amitava Chatterjee , Ekanayake Amerasekera
发明人： Amitava Chatterjee , Ekanayake Amerasekera
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8228 , H01L21/84 , H01L27/02 , H01L27/06 , H01L27/082 , H01L27/092 , H01L27/12 , H01L29/786 , H01L29/74
CPC分类号： H01L27/0262 , H01L21/84 , H01L27/0259 , H01L27/092 , H01L27/12 , H01L27/1203
摘要： A bistable SCR-like switch (41) protects a signal line (65) of an SOI integrated circuit (40) against damage from ESD events. The bistable SCR-like switch (41) is provided by a first and a second transistors (42 and 44) which are formed upon the insulator layer (46) of the SOI circuit (40) and are separated from one another by an insulating region (60). Interconnections (62 and 64) extend between the two transistors (42 and 44) to connect a P region (62) of a first transistor (42) to a P region (54) of the second transistor (44) and an N region (50) of the first transistor (42) to an N region (58) of the second transistor (44). The transistors (42 and 44) may be either bipolar transistors or enhancement type MOSFET transistors. For bipolar transistors, the base of an NPN transistor (42) is connected to the collector of a PNP transistor (44) and the base of the PNP transistor (44) is connected to the collector of the NPN transistor (42). MOSFET transistors are similarity connected, with the intermediate portion of the P-well (43) forming channel region of the N-channel transistor (42) connected to the drain of the P-channel transistor (44), and the N-well (45) forming the channel region of the P-channel transistor (44) connected to the drain of the N-channel transistor (42). Resistors (72 and 74) can be connected between the two transistors (42 and 44) to determine the trigger and holding voltages for the bistable SCR-like switch (41).
摘要翻译：双稳态SCR类开关（41）保护SOI集成电路（40）的信号线（65）免受ESD事件损坏。双稳态SCR型开关（41）由形成在SOI电路（40）的绝缘体层（46）上的第一和第二晶体管（42和44）提供，并且通过绝缘区域彼此分离（60）。互连（62和64）在两个晶体管（42和44）之间延伸以将第一晶体管（42）的P区域（62）连接到第二晶体管（44）的P区域（54）和N区域 50）到第二晶体管（44）的N区（58）。晶体管（42和44）可以是双极晶体管或增强型MOSFET晶体管。对于双极晶体管，NPN晶体管（42）的基极连接到PNP晶体管（44）的集电极，PNP晶体管（44）的基极连接到NPN晶体管（42）的集电极。 MOSFET晶体管是相似的连接，P阱（43）的中间部分形成连接到P沟道晶体管（44）的漏极的N沟道晶体管（42）的沟道区，并且N阱（形成连接到N沟道晶体管（42）的漏极的P沟道晶体管（44）的沟道区。电阻器（72和74）可以连接在两个晶体管（42和44）之间，以确定双稳态SCR状开关（41）的触发和保持电压。

43. 发明授权

US5225702A Silicon controlled rectifier structure for electrostatic discharge protection 失效
标题翻译：可控硅整流器结构，用于静电放电保护
公开(公告)号：US5225702A
公开(公告)日：1993-07-06
申请号：US804271
申请日：1991-12-05
申请人： Amitava Chatterjee
发明人： Amitava Chatterjee
IPC分类号： H01L27/02
CPC分类号： H01L27/0251 , H01L29/87
摘要： A first silicon controlled rectifier structure (220) is provided for electrostatic discharge protection, comprising a lightly doped semiconductor layer (222) having a first conductivity type and a face. A lightly doped region (224) having a second conductivity type opposite the first conductivity type is formed in the semiconductor layer (222) at the face. A first heavily doped region (226) having the second conductivity type is formed laterally within the semiconductor layer (222) at the face and is electrically coupled to a first node (62). A second heavily doped region (230) having the second conductivity type is formed laterally within the lightly doped region (224) and is electrically coupled to a second node (58). A third heavily doped region (228) having the first conductivity type is formed laterally within the lightly doped region (224) to be interposed between the first and second heavily doped regions (226 and 230) and is electrically coupled to the second node (58). A gate insulator region (233) is formed over adjacent regions of the semiconductor layer (222) and of the lightly doped region (224) to be interposed between the first (226) and third (230) heavily doped regions, such that the gate insulator region (233) is formed over a junction (236) between the semiconductor layer (222) and the lightly doped region (224). A polysilicon gate layer (237) is formed over the gate insulator region (233) and is electrically coupled to the first node (62).
摘要翻译：提供用于静电放电保护的第一可控硅整流器结构（220），包括具有第一导电类型和面的轻掺杂半导体层（222）。在半导体层（222）中形成具有与第一导电类型相反的第二导电类型的轻掺杂区（224）。具有第二导电类型的第一重掺杂区域（226）在所述半导体层（222）内在所述面处横向地形成并且电耦合到第一节点（62）。具有第二导电类型的第二重掺杂区域（230）在轻掺杂区域（224）内横向形成，并且电耦合到第二节点（58）。具有第一导电类型的第三重掺杂区域（228）横向地形成在轻掺杂区域（224）内，以被插入在第一和第二重掺杂区域（226和230）之间并且电耦合到第二节点（58））。栅极绝缘体区域（233）形成在半导体层（222）和轻掺杂区域（224）的相邻区域上，以被插入在第一（226）和第三（230）重掺杂区域之间，使得栅极绝缘体区域（233）形成在半导体层（222）和轻掺杂区域（224）之间的结（236）上。多晶硅栅极层（237）形成在栅极绝缘体区域（233）上并且电耦合到第一节点（62）。

44. 发明授权

US08716827B2 Diffusion resistor with reduced voltage coefficient of resistance and increased breakdown voltage using CMOS wells 有权
标题翻译：扩散电阻器具有降低的电阻系数和使用CMOS井的击穿电压增加
公开(公告)号：US08716827B2
公开(公告)日：2014-05-06
申请号：US13609818
申请日：2012-09-11
申请人： Kamel Benaissa , Amitava Chatterjee
发明人： Kamel Benaissa , Amitava Chatterjee
IPC分类号： H01L21/70 , H01L29/00
CPC分类号： H01L21/761 , H01L21/266 , H01L21/823493 , H01L27/0629 , H01L27/0802 , H01L29/66166 , H01L29/8605
摘要： Integrated circuits and manufacturing methods are presented for creating diffusion resistors (101, 103) in which the diffusion resistor well is spaced from oppositely doped wells to mitigate diffusion resistor well depletion under high biasing so as to provide reduced voltage coefficient of resistivity and increased breakdown voltage for high-voltage applications.
摘要翻译：提出了用于产生扩散电阻器（101,103）的集成电路和制造方法，其中扩散电阻器阱与相对掺杂的阱间隔开，以在高偏压下减轻扩散电阻器良好的耗尽，从而提供降低的电阻率电压系数和增加的击穿电压适用于高压应用。

45. 发明授权

US08716097B2 MOS transistors having reduced leakage well-substrate junctions 有权
标题翻译： MOS晶体管具有减少的泄漏良好的衬底结
公开(公告)号：US08716097B2
公开(公告)日：2014-05-06
申请号：US13584016
申请日：2012-08-13
申请人： Terry James Bordelon, Jr. , Amitava Chatterjee
发明人： Terry James Bordelon, Jr. , Amitava Chatterjee
IPC分类号： H01L21/20 , H01L29/93
CPC分类号： H01L21/823892 , H01L21/26513 , H01L27/092 , H01L27/0921 , H01L29/1083 , H01L29/6659 , H01L29/7833
摘要： A Metal-Oxide Semiconductor (MOS) transistor includes a substrate having a topside semiconductor surface doped with a first dopant type having a baseline doping level. A well is formed in the semiconductor surface doped with a second doping type. The well forms a well-substrate junction having a well depletion region. A retrograde doped region is below the well-substrate junction doped with the first dopant type having a peak first dopant concentration of between five (5) and one hundred (100) times above the baseline doping level at a location of the peak first dopant concentration, wherein with zero bias across the well-substrate junction at least (>) ninety (90) % of a total dose of the retrograde doped region is below the bottom of the well depletion region. A gate structure is on the well. Source and drain regions are on opposing sides of the gate structure.
摘要翻译：金属氧化物半导体（MOS）晶体管包括具有掺杂有具有基线掺杂水平的第一掺杂剂类型的顶侧半导体表面的衬底。在掺杂有第二掺杂类型的半导体表面中形成阱。阱形成具有良好耗尽区的良好的衬底结。逆向掺杂区域在掺杂有第一掺杂剂类型的阱衬底结下方具有在峰值第一掺杂剂浓度的位置处具有高于基线掺杂水平的五（5）和百（100）倍之间的峰值第一掺杂浓度其中在穿过阱底衬层的零偏压下，逆向掺杂区域的总剂量的至少（>）九十（90）％低于阱耗尽区的底部。门的结构在井上。源极和漏极区域在栅极结构的相对侧上。

46. 发明授权

US08592900B2 Drain extended CMOS with counter-doped drain extension 有权
标题翻译：漏极扩展扩展CMOS
公开(公告)号：US08592900B2
公开(公告)日：2013-11-26
申请号：US13288690
申请日：2011-11-03
申请人： Philipp Steinmann , Amitava Chatterjee , Sameer Pendharkar
发明人： Philipp Steinmann , Amitava Chatterjee , Sameer Pendharkar
IPC分类号： H01L21/00
CPC分类号： H01L29/66681 , G06F17/5081 , H01L29/0878 , H01L29/1045 , H01L29/161 , H01L29/167 , H01L29/66659 , H01L29/66734 , H01L29/7813 , H01L29/7816 , H01L29/7835 , H01L29/861
摘要： An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS transistor with a drift region containing a first dopant type plus scattering centers. A method for designing an integrated circuit containing a DEMOS transistor with a counter doped drift region.
摘要翻译：一种集成电路，其包含具有包含第一掺杂剂型和散射中心的漂移区的二极管。一种包含DEMOS晶体管的集成电路，其具有包含第一掺杂剂型和散射中心的漂移区。一种用于设计包含具有反掺杂漂移区的DEMOS晶体管的集成电路的方法。

47. 发明授权

US07662688B2 Application of different isolation schemes for logic and embedded memory 有权
标题翻译：不同隔离方案在逻辑和嵌入式存储器中的应用
公开(公告)号：US07662688B2
公开(公告)日：2010-02-16
申请号：US11848187
申请日：2007-08-30
申请人： Kayvan Sadra , Alwin Tsao , Seetharaman Sridhar , Amitava Chatterjee
发明人： Kayvan Sadra , Alwin Tsao , Seetharaman Sridhar , Amitava Chatterjee
IPC分类号： H01L21/00
CPC分类号： H01L21/823807 , H01L21/76229 , H01L21/76237 , H01L21/823481 , H01L21/823493 , H01L21/823878 , H01L21/823892 , H01L27/0207 , H01L27/105 , H01L27/1052
摘要： The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.
摘要翻译：本发明通过提供用于在嵌入式存储器和设备的其他逻辑部分中利用不同隔离方案的机制来促进半导体器件制造。嵌入式存储器部分的隔离机构相对于器件的其它部分通过增加掺杂剂浓度或降低嵌入式存储器阵列的阱区域内的掺杂剂分布的深度来改进。因此，可以采用更小的隔离间隔，从而允许更紧凑的阵列。逻辑部分的隔离机制相对小于嵌入式存储器部分的隔离机制，这允许逻辑的更高的操作速度。

48. 发明申请

US20070287258A1 A METHOD OF MANUFACTURING GATE SIDEWALLS THAT AVOIDS RECESSING 有权
标题翻译：制造门禁的门控方法
公开(公告)号：US20070287258A1
公开(公告)日：2007-12-13
申请号：US11422952
申请日：2006-06-08
申请人： Jong Shik Yoon , Amitava Chatterjee , Haowen Bu
发明人： Jong Shik Yoon , Amitava Chatterjee , Haowen Bu
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L21/2652 , H01L29/665 , H01L29/6653 , H01L29/6659
摘要： A method of manufacturing a semiconductor device comprising removing a first oxide layer deposited over a semiconductor substrate, thereby exposing source and drain regions of the substrate. The first oxide layer is configured as an etch-stop for forming silicon nitride sidewall spacers of a gate structure located adjacent to the source and drain regions. The method further comprises depositing a second oxide layer selectively on the exposed source and drain regions and then removing lateral segments of the silicon nitride sidewall spacers.
摘要翻译：一种制造半导体器件的方法，包括去除沉积在半导体衬底上的第一氧化物层，从而暴露衬底的源极和漏极区域。第一氧化物层被配置为用于形成邻近源极和漏极区的栅极结构的氮化硅侧壁间隔物的蚀刻停止。该方法还包括在暴露的源极和漏极区上选择性地沉积第二氧化物层，然后去除氮化硅侧壁间隔物的侧向部分。

49. 发明授权

US07141468B2 Application of different isolation schemes for logic and embedded memory 有权
标题翻译：不同隔离方案在逻辑和嵌入式存储器中的应用
公开(公告)号：US07141468B2
公开(公告)日：2006-11-28
申请号：US10694237
申请日：2003-10-27
申请人： Kayvan Sadra , Alwin Tsao , Seetharaman Sridhar , Amitava Chatterjee
发明人： Kayvan Sadra , Alwin Tsao , Seetharaman Sridhar , Amitava Chatterjee
IPC分类号： H01L21/00
CPC分类号： H01L21/823807 , H01L21/76229 , H01L21/76237 , H01L21/823481 , H01L21/823493 , H01L21/823878 , H01L21/823892 , H01L27/0207 , H01L27/105 , H01L27/1052
摘要： The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.
摘要翻译：本发明通过提供用于在嵌入式存储器和设备的其他逻辑部分中利用不同隔离方案的机制来促进半导体器件制造。嵌入式存储器部分的隔离机构相对于器件的其它部分通过增加掺杂剂浓度或降低嵌入式存储器阵列的阱区域内的掺杂剂分布的深度来改进。因此，可以采用更小的隔离间隔，从而允许更紧凑的阵列。逻辑部分的隔离机制相对小于嵌入式存储器部分的隔离机制，这允许逻辑的更高的操作速度。

50. 发明授权

US07098099B1 Semiconductor device having optimized shallow junction geometries and method for fabrication thereof 有权
标题翻译：具有优化的浅结几何形状的半导体器件及其制造方法
公开(公告)号：US07098099B1
公开(公告)日：2006-08-29
申请号：US11064583
申请日：2005-02-24
申请人： Brian E. Hornung , Jong Yoon , Deborah J. Riley , Amitava Chatterjee
发明人： Brian E. Hornung , Jong Yoon , Deborah J. Riley , Amitava Chatterjee
IPC分类号： H01L21/8238
CPC分类号： H01L21/823864 , H01L21/823814
摘要： The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). In one embodiment, the method includes growing an oxide layer 120 from a substrate 104, 106 over a first dopant region 122 and a second dopant region 128, implanting a first dopant through the oxide layer 120, into the substrate 104 in the first dopant region 122, and adjacent a gate structure 114, and substantially removing the oxide layer 120 from the substrate within the second dopant region 128. Subsequent to the removal of the oxide layer 120 in the second dopant region 128, a second dopant that is opposite in type to the first dopant is implanted into the substrate 106 and within the second dopant region 128 and adjacent a gate structure 114.
摘要翻译：本发明在一个实施例中提供一种制造半导体器件（100）的方法。在一个实施例中，该方法包括在第一掺杂剂区域122和第二掺杂剂区域128之上从衬底104,106生长氧化物层120，将第一掺杂剂注入到氧化物层120中，将第一掺杂剂注入第一掺杂剂区域并且与栅极结构114相邻，并且在第二掺杂剂区域128内基本上从衬底去除氧化物层120。在第二掺杂区域128中除去氧化物层120之后，将与第一掺杂剂类型相反的第二掺杂剂注入到衬底106中并且在第二掺杂剂区域128内并且与栅极结构114相邻。

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