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41. 发明授权

US07295077B2 Multi-frequency clock synthesizer 有权
标题翻译：多频时钟合成器
公开(公告)号：US07295077B2
公开(公告)日：2007-11-13
申请号：US11270954
申请日：2005-11-10
申请人： Axel Thomsen , Yunteng Huang , Jerrell P. Hein , Michael Petrowski, III
发明人： Axel Thomsen , Yunteng Huang , Jerrell P. Hein , Michael Petrowski, III
IPC分类号： H03B21/00
CPC分类号： H03L7/23 , H03L7/0898 , H03L7/197 , H03L7/1976
摘要： A phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal, a phase detector circuit coupled to receive the timing reference signal, a controllable oscillator circuit controlled according to an output of the phase detector circuit, and a feedback divider circuit having an output coupled to the phase detector and an input coupled to the controllable oscillator circuit. The phase-locked loop circuit is coupled to output one of a plurality of output signals having an arbitrary frequency relationship to each other according to a frequency selection mechanism, the frequency selection mechanism including one or more input terminals coupled to control a divide ratio of the feedback divider circuit. The frequency selection mechanism selects one of a plurality of stored values. The selected stored value controls, at least in part, a divide ratio of the feedback divider circuit, thereby providing a pin programmable device capable of selecting among output frequencies having an arbitrary relationship to each other.
摘要翻译：锁相环（PLL）电路包括用于接收定时参考信号的输入端，耦合以接收定时参考信号的相位检测器电路，根据相位检测器电路的输出控制的可控振荡器电路，以及反馈分配器电路具有耦合到相位检测器的输出端和耦合到可控振荡器电路的输入端。锁相环电路根据频率选择机构耦合到输出具有任意频率关系的多个输出信号中的一个，所述频率选择机构包括一个或多个输入端，用于控制所述频率选择机构的分频比反馈分频电路。频率选择机构选择多个存储值中的一个。选择的存储值至少部分地控制反馈分频器电路的分频比，从而提供能够在彼此具有任意关系的输出频率之间进行选择的引脚可编程器件。

42. 发明授权

US06686803B1 Integrated circuit incorporating circuitry for determining which of at least two possible frequencies is present on an externally provided reference signal and method therefor 有权
标题翻译：集成电路并入电路，用于确定至少两个可能频率中的哪一个在外部提供的参考信号上以及其方法
公开(公告)号：US06686803B1
公开(公告)日：2004-02-03
申请号：US09902543
申请日：2001-07-10
申请人： Michael H. Perrott , Jerrell P. Hein , Rex T. Baird
发明人： Michael H. Perrott , Jerrell P. Hein , Rex T. Baird
IPC分类号： H03L7089
CPC分类号： H03L7/091 , H03L7/087 , H03L7/095 , H04L7/0004 , H04L7/033
摘要： An internal frequency reference, such as a VCO used in a PLL, having a free-running frequency fairly well controlled within a predictable range, is used as a rough frequency reference to determine, for an externally-provided frequency reference signal, which of a finite number of discrete frequencies is currently received. The VCO has a frequency range which varies less, as a percentage, than the ratio between possible reference frequency values. Consequently, the VCO is used as a frequency reference to measure the frequency reference signal. An internal signal is generated to indicate to remaining circuitry which of the possible reference frequencies is actually being provided, without requiring use of any dedicated input pins to receive a select signal. An integrated circuit device may be configured for different modes of operation as a function of which reference frequency is provided to the device. Moreover, if one of the available reference clock frequencies is chosen to correspond to an internal test mode, the device may be placed in a test mode without requiring any additional dedicated input pins for that purpose, either.
摘要翻译：使用在PLL中使用的具有在可预测范围内相当好地控制的自由运行频率的内部频率参考，例如在PLL中使用的VCO，作为粗略的频率参考，以确定对于外部提供的频率参考信号中的哪一个当前接收到有限数量的离散频率。 VCO的频率范围比可能的参考频率值之间的比例变化更小，百分比。因此，VCO被用作频率参考以测量频率参考信号。产生内部信号以指示剩余电路实际上提供哪些可能的参考频率，而不需要使用任何专用输入引脚来接收选择信号。集成电路设备可以被配置为不同的操作模式，作为向设备提供参考频率的功能。此外，如果选择可用的参考时钟频率之一以对应于内部测试模式，则该设备也可以放置在测试模式中，而不需要用于该目的的任何额外的专用输入引脚。

43. 发明授权

US06567521B1 Subscriber loop interface circuitry having bifurcated common mode control 失效
标题翻译：具有分叉共模控制的用户环路接口电路
公开(公告)号：US06567521B1
公开(公告)日：2003-05-20
申请号：US09375911
申请日：1999-08-17
申请人： Jerrell P. Hein
发明人： Jerrell P. Hein
IPC分类号： H04M100
CPC分类号： H04M19/02
摘要： A subscriber loop interface circuit having bifurcated common mode control loops includes a DC common mode control for controlling tip and ring DC common mode characteristics, and an AC common mode control for controlling tip and ring AC common mode characteristics, wherein the AC and DC common mode controls are independent. In one embodiment, the DC common mode control includes a tip current source for generating a tip current, idt, and a ring current source for generating a ring current, idr, Each of idt and idr is proportional to a difference between a DC tip voltage (TIPDC) and a control voltage (Vcmcontrol). Thus, in one embodiment, idt=gdt(TIPDC−Vcmcontrol), and idr=gdr(TIPDC−Vcmcontrol). In one embodiment, the AC common mode control includes a tip current source for generating a tip current, iat, and a ring current source for generating a ring current, iar. Each of iat and iar is a function of an AC tip voltage (TIPAC) and an AC ring voltage (RINGAC). The currents iat and iar are proportional to a difference between a first gain term times an AC longitudinal voltage and a second gain term times the AC tip voltage. Thus in one embodiment, the AC tip current source provides the current i at = g at1 ⁢ ( TIPAC + RINGAC 2 ) - g at2 · TIPAC . Similarly, the AC ring current source provides the current i ar = g ar1 ⁢ ( TIPAC + RINGAC 2 ) - g ar2 · TIPAC . The second gain term in each AC current control equation enables cancellation of unwanted contributions from the DC control loop in the audio band.
摘要翻译：具有分叉共模控制回路的用户环路接口电路包括用于控制尖端和环形DC共模特性的DC共模控制，以及用于控制尖端和环路AC共模特性的AC共模控制，其中AC和DC共模控制是独立的。在一个实施例中，DC共模控制包括用于产生尖端电流的尖端电流源，以及用于产生环形电流idr的环形电流源，idt和idr中的每一个与直流尖端电压（TIPDC）和控制电压（Vcmcontrol）。因此，在一个实施例中，idt = gdt（TIPDC-Vcmcontrol）和idr = gdr（TIPDC-Vcmcontrol）。在一个实施例中，AC共模控制包括用于产生尖端电流的尖端电流源和用于产生环形电流的环形电流源。 iat和iar中的每一个都是AC尖端电压（TIPAC）和AC环形电压（RINGAC）的函数。电流iat和iar与第一增益项乘以AC纵向电压和第二增益项乘以AC尖端电压之间的差成比例。因此，在一个实施例中，AC尖端电流源类似地提供电流，AC环电流源提供电流。每个AC电流控制方程式中的第二增益项使得能够消除来自音频带中的DC控制环的不需要的贡献。

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