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41. 发明授权

US06624651B1 Kerf circuit for modeling of BEOL capacitances 有权
标题翻译：用于BEOL电容建模的Kerf电路
公开(公告)号：US06624651B1
公开(公告)日：2003-09-23
申请号：US09684849
申请日：2000-10-06
申请人： David M. Fried , Peter A. Habitz
发明人： David M. Fried , Peter A. Habitz
IPC分类号： G01R3126
CPC分类号： G01R31/006
摘要： A kerf circuit for modeling of Back End Of Line (BEOL) capacitances is disclosed. The kerf circuit contains a clock circuit connected to a number of capacitance testing circuits. Each capacitance testing circuit acts a “bay” that can be configured to test one particular capacitance. The clock circuit allows the capacitance testing circuits to charge and discharge the capacitive structures being tested. By having a number of different capacitance testing circuits, capacitances of many different structures may be tested at one time. This is particularly true if the kerf circuit is repeated several or many times, with each different kerf circuit containing different capacitive testing circuits that themselves contain different capacitive structures. The kerf circuit interfaces to testing equipment through pads. The pads connect to each capacitive testing circuit and allow capacitance measurements to be performed by measuring current.
摘要翻译：公开了一种用于线路后端（BEOL）电容建模的切口电路。切口电路包含连接到多个电容测试电路的时钟电路。每个电容测试电路都作为一个“间隔”，可以配置为测试一个特定的电容。时钟电路允许电容测试电路对被测试的电容结构进行充电和放电。通过具有多个不同的电容测试电路，可以一次测试许多不同结构的电容。如果切割电路重复数次或多次，则特别如此，每个不同的切屑回路包含不同的电容测试电路，它们本身包含不同的电容结构。切口电路通过焊盘与测试设备接口。焊盘连接到每个电容测试电路，并通过测量电流来进行电容测量。

42. 发明授权

US06519752B1 Method of performing parasitic extraction for a multi-fingered transistor 失效
标题翻译：对多指晶体管进行寄生提取的方法
公开(公告)号：US06519752B1
公开(公告)日：2003-02-11
申请号：US09561096
申请日：2000-04-28
申请人： William C. Bakker , L. William Dewey, III , Peter A. Habitz , Judith H. McCullen , Edward W. Seibert , Michael J. Sullivan
发明人： William C. Bakker , L. William Dewey, III , Peter A. Habitz , Judith H. McCullen , Edward W. Seibert , Michael J. Sullivan
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A method and structure for performing parasitic extraction for a multi-fingered device comprising of establishing a maximum processing width of a finger of the device, dividing fingers of the device that exceed the maximum width into sub-fingers, determining whether ones of the fingers and the sub-fingers have similar characteristics, combining ones of the fingers and the sub-fingers that have similar characteristics into combined fingers, and extracting parasitic values from the fingers, the sub-fingers and the combined fingers.
摘要翻译：一种用于对多指装置执行寄生提取的方法和结构，包括：建立装置的手指的最大处理宽度，将超过最大宽度的装置的手指分成子手指，确定手指中是否有手指子手指具有类似的特征，将具有类似特征的手指和子手指组合成组合手指，并从手指，子手指和组合手指中提取寄生值。

43. 发明授权

US06460167B1 Efficient system for multi-level shape interactions 失效
标题翻译：用于多层次形状相互作用的高效系统
公开(公告)号：US06460167B1
公开(公告)日：2002-10-01
申请号：US09559800
申请日：2000-04-27
申请人： L. William Dewey, III , Peter A. Habitz
发明人： L. William Dewey, III , Peter A. Habitz
IPC分类号： G06F1750
CPC分类号： G06F17/5081
摘要： A structure and method for evaluating an integrated circuit design includes adding a superseding layer of the integrated circuit design over a previous layer of the integrated circuit structure, identifying database pointers for regions and edges within the superseding layer and the previous layer, removing database pointers for regions of the previous layer overlapped by the superseding layer, classifying the superseding layer and the previous layer as the previous layer, and repeating the method until all layers of the integrated circuit are evaluated.
摘要翻译：用于评估集成电路设计的结构和方法包括在集成电路结构的先前层上添加集成电路设计的替代层，识别替代层和先前层中的区域和边缘的数据库指针，去除数据库指针上一层的区域与替代层重叠，将取代层和先前层分类为上一层，并重复该方法直到评估集成电路的所有层。

44. 发明授权

US5761080A Method and apparatus for modeling capacitance in an integrated circuit 失效
标题翻译：用于对集成电路中的电容进行建模的方法和装置
公开(公告)号：US5761080A
公开(公告)日：1998-06-02
申请号：US561647
申请日：1995-11-22
申请人： William F. DeCamp , John J. Ellis-Monaghan , Peter A. Habitz , Edward W. Seibert
发明人： William F. DeCamp , John J. Ellis-Monaghan , Peter A. Habitz , Edward W. Seibert
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , Y10S706/921
摘要： According to the present embodiment, a method for calculating the parasitic capacitance in a semiconductor device is disclosed. According to the preferred method, a layout file containing the shapes of a semiconductor device is provided. The dimensions of the layout file are then adjusted to wafer dimensions so as reflect actual production devices. The shapes of the layout file are then partitioned into simpler shapes, typically abutted rectangles, called tiles. Each tile is then decomposed into overlap and fringe capacitance components, each component having a uniform capacitance environment with respect to its capacitance elements. The parasitic capacitance of the semiconductor device can thus be accurately computed, with an efficient use of resources. Additionally the preferred embodiment is easily adaptable to a wide range of technology types.
摘要翻译：根据本实施例，公开了一种用于计算半导体器件中的寄生电容的方法。根据优选方法，提供了包含半导体器件的形状的布局文件。然后将布局文件的尺寸调整为晶圆尺寸，以反映实际的生产设备。然后，布局文件的形状被分割成更简单的形状，通常是称为块的邻接矩形。然后，每个瓦片被分解成重叠和边缘电容分量，每个部件相对于其电容元件具有均匀的电容环境。因此，可以有效利用资源来准确地计算半导体器件的寄生电容。此外，优选实施例容易适应于广泛的技术类型。

45. 发明授权

US08560989B2 Statistical clock cycle computation 有权
标题翻译：统计时钟周期计算
公开(公告)号：US08560989B2
公开(公告)日：2013-10-15
申请号：US13311832
申请日：2011-12-06
申请人： Nathan Buck , Brian Dreibelbis , John P. Dubuque , Eric A. Foreman , James C. Gregerson , Peter A. Habitz , Jeffrey G. Hemmett , Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Michael H. Wood , Vladimir Zolotov
发明人： Nathan Buck , Brian Dreibelbis , John P. Dubuque , Eric A. Foreman , James C. Gregerson , Peter A. Habitz , Jeffrey G. Hemmett , Debjit Sinha , Natesan Venkateswaran , Chandramouli Visweswariah , Michael H. Wood , Vladimir Zolotov
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/10 , G06F2217/62
摘要： Systems and methods for statistical clock cycle computation and closing timing of an integrated circuit design to a maximum clock cycle or period. The method includes loading a design and timing model for at least one circuit path of an integrated circuit or a region of the integrated circuit into a computing device. The method further includes performing a statistical static timing analysis (SSTA) of the at least one circuit path using the loaded design and timing model to obtain slack canonical data. The method further includes calculating a maximum circuit clock cycle for the integrated circuit or the specified region of the integrated circuit in linear canonical form based upon the slack canonical data obtained from the SSTA.
摘要翻译：将集成电路设计的统计时钟周期计算和闭合时序的系统和方法设计到最大时钟周期或周期。该方法包括将用于集成电路或集成电路的区域的至少一个电路路径的设计和定时模型加载到计算设备中。该方法还包括使用加载的设计和定时模型来执行至少一个电路路径的统计静态时序分析（SSTA），以获得松散的规范数据。该方法还包括基于从SSTA获得的松弛规范数据，以线性规范形式计算集成电路或集成电路的指定区域的最大电路时钟周期。

46. 发明授权

US08468483B2 Method, system and program storage device for performing a parameterized statistical static timing analysis (SSTA) of an integrated circuit taking into account setup and hold margin interdependence 失效
标题翻译：用于执行集成电路的参数化统计静态时序分析（SSTA）的方法，系统和程序存储装置，其考虑到建立和保持边际相互依赖性
公开(公告)号：US08468483B2
公开(公告)日：2013-06-18
申请号：US13279373
申请日：2011-10-24
申请人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang , Vladimir Zolotov
发明人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang , Vladimir Zolotov
IPC分类号： G06F9/455
CPC分类号： G06F17/5031 , G06F2217/84
摘要： In embodiments of a statistical static timing analysis (SSTA) method, system and program storage device, the interdependence between the setup time and hold time margins of a circuit block (e.g., a latch, flip-flop, etc., which requires the checking of setup and hold timing constraints) is determined, taking into account possible variations in multiple parameters (e.g., using a variation-aware characterizing technique). A parameterized statistical static timing analysis (SSTA) of a circuit incorporating the circuit block is performed in order to determine, in statistical parameterized form, setup and hold times for the circuit block. Based on the interdependence between the setup and hold time margins, setup and hold time constraints can be determined in statistical parameterized form. Finally, the setup and hold times determined during the SSTA can be checked against the setup and hold time constraints to determine, if the time constraints are violated or not and to what degree.
摘要翻译：在统计静态时序分析（SSTA）方法，系统和程序存储装置的实施例中，需要检查的电路块（例如，锁存器，触发器等）的建立时间和保持时间裕度之间的相互依赖关系确定设置和保持时序约束），同时考虑到多个参数的可能变化（例如，使用变异感知特性技术）。执行结合电路块的电路的参数化统计静态时序分析（SSTA），以便以统计参数化形式确定电路块的建立和保持时间。基于设置和保持时间间隔之间的相互依赖性，可以以统计参数化形式确定建立和保持时间约束。最后，可以根据建立和保持时间约束来检查SSTA期间确定的建立和保持时间，以确定是否违反时间限制，以及在何种程度上。

47. 发明授权

US08448110B2 Method to reduce delay variation by sensitivity cancellation 失效
标题翻译：通过灵敏度消除来减少延迟变化的方法
公开(公告)号：US08448110B2
公开(公告)日：2013-05-21
申请号：US12625139
申请日：2009-11-24
申请人： Peter A. Habitz , Eric A. Foreman , Gustavo E. Tellez
发明人： Peter A. Habitz , Eric A. Foreman , Gustavo E. Tellez
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5031 , G06F2217/12 , G06F2217/84 , Y02P90/265
摘要： A method receives an initial circuit design. The circuit design includes at least one path having at least one beginning point comprising a source, at least one ending point comprising a sink, and one or more circuit elements between the source and the sink. The method evaluates timing performance parameter sensitivities to manufacturing variations of each of the elements to identify how much each element will increase or decrease the timing performance parameter of the path for each change in each manufacturing variable associated with manufacturing the elements. Further, the method alters the elements within the path until elements that produce positive changes to the timing performance parameter for a given manufacturing variable change approximately equals (in magnitude) elements that produce negative changes to the timing performance parameter for the given manufacturing variable change, to produce an altered circuit design.
摘要翻译：一种方法接收初始电路设计。该电路设计包括至少一个路径，该至少一个路径具有包括源的至少一个起始点，包括宿的至少一个终点以及源和宿之间的一个或多个电路元件。该方法评估每个元件的制造变化的时序性能参数灵敏度，以识别每个元件将增加或减少与制造元件相关联的每个制造变量中的每个变化的路径的时序性能参数。此外，该方法改变路径内的元素，直到产生对于给定制造变量的定时性能参数的正变化的元素大致等于（在大小上）元素，该元素对于给定的制造变量变化而对定时性能参数产生负变化，以产生改变的电路设计。

48. 发明授权

US08239810B2 Method and system for optimizing a device with current source models 有权
标题翻译：使用当前源模型优化设备的方法和系统
公开(公告)号：US08239810B2
公开(公告)日：2012-08-07
申请号：US12944480
申请日：2010-11-11
申请人： Soroush Abbaspour , Peter Feldmann , Peter A. Habitz , Safar Hatami
发明人： Soroush Abbaspour , Peter Feldmann , Peter A. Habitz , Safar Hatami
IPC分类号： G06F9/455 , G06F17/50
CPC分类号： G06F17/5031 , G06F2217/80 , G06F2217/84
摘要： A method for optimizing a circuit includes at least a first branch and a second branch includes defining an objective function using a shape of waveforms measured at a timing point in each branch, and optimizing the objective function to minimize a variance of clock skew of the first branch and the second branch across different process voltage temperature values.
摘要翻译：一种用于优化电路的方法包括至少第一分支和第二分支，包括使用在每个分支中的定时点测量的波形的形状来定义目标函数，以及优化目标函数以最小化第一分支的时钟偏差的方差分支和第二分支横跨不同的过程电压温度值。

49. 发明申请

US20120084066A1 SYSTEM AND METHOD FOR EFFICIENT MODELING OF NPSKEW EFFECTS ON STATIC TIMING TESTS 有权
标题翻译：用于有效建模静态时间测试的NPSKEW效应的系统和方法
公开(公告)号：US20120084066A1
公开(公告)日：2012-04-05
申请号：US12894286
申请日：2010-09-30
申请人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue X. Wang
发明人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue X. Wang
IPC分类号： G06F17/50
CPC分类号： G06F13/105 , G06F11/261 , G06F17/50 , G06F17/5036
摘要： A computer-implemented method that simulates NPskew effects on a combination NFET (Negative Field Effect Transistor)/PFET (Positive Field Effect Transistor) semiconductor device using slew perturbations includes performing a timing test by a computing device, by: (1) evaluating perturb slews in Strong N/Weak P directions on the combination semiconductor device for a timing test result; (2) evaluation perturb slews in Weak N/Strong P directions on the combination semiconductor device for a timing test result; and (3) evaluating unperturbed slews in a balanced condition on the combination semiconductor device for a timing test result. After each test is performed, a determination is made as to which evaluation of the perturbed and unperturbed slews produces a most conservative timing test result for the combination semiconductor device. An NPskew effect adjusted timing test result is finally output based on determining the most conservative timing test result.
摘要翻译：使用摆动扰动模拟组合NFET（负场效应晶体管）/ PFET（正场效应晶体管）/ PFET（正场效应晶体管））半导体器件的NPskew效应的计算机实现的方法包括通过以下方式执行计算设备的定时测试：（1）评估干扰压摆在组合半导体器件上以强N /弱P方向进行定时测试结果; （2）组合半导体器件的评估扰动在弱N /强P方向上的时序测试结果; 和（3）在组合半导体器件上对平衡状态下的非扰动压摆进行定时测试结果。在执行每个测试之后，确定扰动和未扰动的压摆的哪个评估对组合半导体器件产生最保守的定时测试结果。基于确定最保守的定时测试结果，最终输出NPskew效果调整的定时测试结果。

50. 发明授权

US08141012B2 Timing closure on multiple selective corners in a single statistical timing run 有权
标题翻译：在单个统计计时运行中，在多个选择性角落定时关闭
公开(公告)号：US08141012B2
公开(公告)日：2012-03-20
申请号：US12549061
申请日：2009-08-27
申请人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Susan K. Lichtensteiger , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang
发明人： Nathan C. Buck , Brian M. Dreibelbis , John P. Dubuque , Eric A. Foreman , Peter A. Habitz , Jeffrey G. Hemmett , Susan K. Lichtensteiger , Natesan Venkateswaran , Chandramouli Visweswariah , Xiaoyue Wang
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F2217/84
摘要： An approach for covering multiple selective timing corners in a single statistical timing run is described. In one embodiment, a single statistical timing analysis is run on the full parameter space that covers unlimited process parameters/environment conditions. Results from the statistical timing analysis are projected for selected corners. Timing closure is performed on the corners having the worst slacks.
摘要翻译：描述了在单个统计时序运行中覆盖多个选择性定时角的方法。在一个实施例中，在涵盖无限制过程参数/环境条件的完整参数空间上运行单个统计时序分析。统计时间分析的结果预计为所选角。在具有最差松弛度的角落上进行定时关闭。

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