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41. 发明申请

US20120166891A1 TWO-LEVEL SYSTEM MAIN MEMORY 有权
标题翻译：两级系统主要内存
公开(公告)号：US20120166891A1
公开(公告)日：2012-06-28
申请号：US12976545
申请日：2010-12-22
申请人： Eric J. Dahlen , Glenn J. Hinton , Raj K. Ramanujan
发明人： Eric J. Dahlen , Glenn J. Hinton , Raj K. Ramanujan
IPC分类号： G06F11/16 , G06F12/00
CPC分类号： G06F3/0611 , G06F3/0647 , G06F3/0685 , G06F11/0766 , G06F12/0246 , G06F12/0638 , G06F12/0868 , G06F12/0893 , G06F2212/1024 , G06F2212/313 , G06F2212/7203 , G06F2212/7208 , G06F2212/7209 , G06F2212/7211 , G11C14/009
摘要： Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory.The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.
摘要翻译：本发明的实施例描述了包括两级存储器的系统主存储器，其包括系统盘级存储器的缓存子集。该主存储器包括包括由易失性存储器构成的存储器的“近存储器”，以及包括比近存储器更大和更慢的易失性或非易失性存储器存储器的“远存储器”。远端存储器被呈现为主机OS的“主存储器”，而近端存储器是对于对OS是透明的远存储器的高速缓存，因此与OS显示与现有技术主存储器解决方案相同的高速缓存。两级存储器的管理可以通过经由主机CPU执行的逻辑和模块的组合来完成。靠近存储器可以通过高带宽，低延迟的方式耦合到主机系统CPU，用于有效处理。远存储器可以经由低带宽，高延迟装置耦合到CPU。

42. 发明授权

US4825412A Lockout registers 失效
标题翻译：锁定寄存器
公开(公告)号：US4825412A
公开(公告)日：1989-04-25
申请号：US176448
申请日：1988-04-01
申请人： David J. Sager , Raj K. Ramanujan , Jeffrey L. Bell
发明人： David J. Sager , Raj K. Ramanujan , Jeffrey L. Bell
IPC分类号： G06F12/10 , G11C15/00
CPC分类号： G06F12/1045
摘要： A cache memory system in a data processor that has a main memory and a processing unit, the cache memory system including a virtually addressed storage cache. This virtually addressed storage cache is connected to the main memory for storing in storage cache locations preselected portions of data from the main memory. Each cache location includes a valid indicator to indicate the data in the cache location is current. A translation buffers is coupled to the storage cache, and translates a virtual address to a physical address. The backmap is coupled to the storage cache and the translation buffer, and invalidates data in the storage cache by generating an invalidate index to the cache location at which a valid indicator is to be cleared only when data in the storage cache is to be invalidated. The cache memory system includes at least one lockout register for storing addresses for data which may exist in more than one storage location. The backmap invalidates all copies of the data in the storage cache after every reference to data in the storage cache using an address in the lockout register.
摘要翻译：具有主存储器和处理单元的数据处理器中的高速缓冲存储器系统，所述高速缓存存储器系统包括虚拟地寻址的存储高速缓存。该虚拟寻址的存储高速缓存连接到主存储器，用于存储来自主存储器的数据的预选部分的存储缓存位置。每个高速缓存位置包括一个有效的指示符，以指示高速缓存位置中的数据是当前的。翻译缓冲器耦合到存储高速缓存，并将虚拟地址转换为物理地址。背景图被耦合到存储高速缓存和翻译缓冲器，并且通过仅在存储高速缓存中的数据被无效时，才通过生成有效指示符被清除的高速缓存位置的无效索引来使存储高速缓存中的数据无效。高速缓冲存储器系统包括至少一个锁定寄存器，用于存储可能存在于多于一个存储位置的数据的地址。每次使用锁定寄存器中的地址对存储缓存中的数据进行引用之后，后台映射将使存储缓存中的所有数据副本无效。

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