专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

41. 发明申请

US20080209095A1 STRUCTURE FOR REDUCING LATENCY ASSOCIATED WITH READ OPERATIONS IN A MEMORY SYSTEM 失效
标题翻译：用于减少与存储器系统中的读操作相关的延迟的结构
公开(公告)号：US20080209095A1
公开(公告)日：2008-08-28
申请号：US12114787
申请日：2008-05-04
申请人： JAMES J. ALLEN , Steven K. Jenkins , James A. Mossman , Michael R. Trombley
发明人： JAMES J. ALLEN , Steven K. Jenkins , James A. Mossman , Michael R. Trombley
IPC分类号： G06F13/36
CPC分类号： G06F13/1689
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a processor memory system, which may include a processor and a memory controller in communication with the processor through a bus. The memory controller may include a delay circuit to receive an early read indicator corresponding to read data from a memory, the delay circuit to delay the early read indicator in accordance with a pre-determined delay such that the early read indicator is passed to the bus in advance of the read data, and a delay adjustment circuit to dynamically adjust the pre-determined delay associated with the delay circuit responsive to a change in operational speed of the processor or the bus.
摘要翻译：提供了体现在用于设计，制造和/或测试设计的机器可读存储介质中的设计结构。设计结构通常包括处理器存储器系统，其可以包括处理器和通过总线与处理器通信的存储器控制器。存储器控制器可以包括延迟电路，用于接收对应于来自存储器的读取数据的早期读取指示符，延迟电路根据预定的延迟来延迟早期读取指示符，使得早期读取指示符被传递到总线以及延迟调整电路，用于响应于处理器或总线的操作速度的变化来动态地调整与延迟电路相关联的预定延迟。

42. 发明授权

US5471626A Variable stage entry/exit instruction pipeline 失效
标题翻译：变量进入/退出指令流水线
公开(公告)号：US5471626A
公开(公告)日：1995-11-28
申请号：US879651
申请日：1992-05-06
申请人： Michael J. Carnevale , Ronald N. Kalla , Gary P. McClannahan , Michael R. Trombley
发明人： Michael J. Carnevale , Ronald N. Kalla , Gary P. McClannahan , Michael R. Trombley
IPC分类号： G06F9/28 , G06F9/38
CPC分类号： G06F9/3873 , G06F9/3867
摘要： An instruction pipeline includes a sequence of interconnected pipeline stages, each stage dedicated to one of several operations executed on data in a digital processing device. Control words govern execution of the operations as they progress through the pipeline. The pipeline stages, as well as the pipeline entry and exit, are interconnected in a manner that permits each control word to enter and exit the pipeline at any one of the stages, and to skip any stages in which the control word will not govern any operations on data. On occasion, this permits a control word to bypass another control word which originally preceded it in the pipeline, thus to reverse the order of the two control words. A mapping field in each control word predetermines its route through the instruction pipeline, one bit of the map field corresponding to each pipeline stage. The route of each control word further is controlled by arbitration logic to resolve contentions among control words for particular pipeline stages, and to insure against a reversal in control word order when such reversal might produce an error. Each pipeline stage is a data register configured to accommodate one control word at a time. Succeeding stage registers are selectively reduced in length to eliminate selected segments and bit positions, thereby deleting from each control word certain bits and multiple bit fields executed in preceding stages.
摘要翻译：指令流水线包括一系列互连的流水线级，各级专用于在数字处理装置中对数据执行的若干操作之一。控制字管理操作在管道进行时的执行。流水线阶段以及管道进出口以允许每个控制字在任何一个阶段进入和退出管道的方式相互连接，并且跳过控制字不管理任何阶段的任何阶段数据操作。有时，这允许一个控制字绕过原来在其前面的另一个控制字，从而颠倒两个控制字的顺序。每个控制字中的映射字段预先确定其通过指令流水线的路由，对应于每个流水线级的映射字段的一位。每个控制字的路由进一步由仲裁逻辑控制，以解决特定流水线级的控制字之间的争用，并且当这种反转可能产生错误时，确保防止控制字顺序的反转。每个流水线级是配置为一次容纳一个控制字的数据寄存器。成功的级寄存器被选择性地减小长度以消除所选择的段和位位置，从而从每个控制字删除某些位和在先前阶段执行的多个位字段。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式