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41. 发明授权

US5075679A Analog/digital converter configuration with sigma-delta modulators 失效
标题翻译：具有SIGMA-DELTA调制器的模拟/数字转换器配置
公开(公告)号：US5075679A
公开(公告)日：1991-12-24
申请号：US625207
申请日：1990-12-10
申请人： Lajos Gazsi
发明人： Lajos Gazsi
IPC分类号： H03M3/04 , H03M3/02
CPC分类号： H03M3/488
摘要： An analog/digital converter configuration includes sigma-delta modulators being triggered by an analog input signal and emitting digital output signals at a predetermined sampling rate. The sigma-delta modulators have input circuits with amplification factors. Amplifiers are each connected upstream of a respective one of the sigma-delta modulators. First sampling rate reducers are each connected downstream of a respective one of the sigma-delta modulators. Damping elements are each connected downstream of a respective one of the first sampling rate reducers. Each of the damping elements have a damping factor equal to the inverse of the amplification factor occurring in the input circuit of a corresponding one of the sigma-delta modulators. A priority logic is connected downstream of the damping elements. A second sampling rate reducer is connected downstream of the priority logic. An output is connected downstream of the second sampling rate reducer. The priority logic switches a signal from the first sampling rate reducers to the output after evaluation of signals from the first sampling rate reducers.
摘要翻译：模拟/数字转换器配置包括由模拟输入信号触发并以预定采样率发射数字输出信号的Σ-Δ调制器。 Σ-Δ调制器具有放大因子的输入电路。放大器各自连接在相应的一个Σ-Δ调制器的上游。第一采样率降低器各自连接在相应的一个Σ-Δ调制器的下游。阻尼元件各自连接在第一采样率降低器中的相应一个的下游。每个阻尼元件具有等于在对应的一个Σ-Δ调制器的输入电路中出现的放大因子的倒数的阻尼因子。优先级逻辑连接在阻尼元件的下游。第二个采样率降低器连接在优先级逻辑的下游。输出连接在第二采样率降低器的下游。在对来自第一采样率降低器的信号进行评估之后，优先逻辑将信号从第一采样率减速器切换到输出。

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