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41. 发明授权

US09224748B2 Method of forming spaced-apart charge trapping stacks 有权
标题翻译：形成间隔开的电荷捕获堆叠的方法
公开(公告)号：US09224748B2
公开(公告)日：2015-12-29
申请号：US12696409
申请日：2010-01-29
申请人： Hiroyuki Kinoshita , Ning Cheng , Minghao Shen
发明人： Hiroyuki Kinoshita , Ning Cheng , Minghao Shen
IPC分类号： H01L27/115
CPC分类号： H01L27/11563 , H01L27/115 , H01L27/11568
摘要： Methods are provided for fabricating memory devices. A method comprises fabricating charge-trapping stacks overlying a silicon substrate and forming bit line regions in the substrate between the charge trapping stacks. Insulating elements are formed overlying the bit line regions between the stacks. The charge-trapping stacks are etched to form two complementary charge storage nodes and to expose portions of the silicon substrate. Silicon is grown on the exposed silicon substrate by selective epitaxial growth and is oxidized. A control gate layer is formed overlying the complementary charge storage nodes and the oxidized epitaxially-grown silicon.
摘要翻译：提供了用于制造存储器件的方法。一种方法包括制造覆盖在硅衬底上的电荷俘获堆叠，并在电荷俘获堆叠之间形成衬底中的位线区域。绝缘元件形成在堆叠之间的位线区域之上。电荷俘获堆被蚀刻以形成两个互补电荷存储节点并暴露硅衬底的部分。硅通过选择性外延生长在暴露的硅衬底上生长并被氧化。形成覆盖互补电荷存储节点和氧化的外延生长硅的控制栅层。

42. 发明授权

US09159568B2 Method for fabricating memory cells having split charge storage nodes 有权
标题翻译：用于制造具有分离电荷存储节点的存储单元的方法
公开(公告)号：US09159568B2
公开(公告)日：2015-10-13
申请号：US11639666
申请日：2006-12-15
申请人： Chungho Lee , Wei Zheng , Chi Chang , Unsoon Kim , Hiroyuki Kinoshita
发明人： Chungho Lee , Wei Zheng , Chi Chang , Unsoon Kim , Hiroyuki Kinoshita
IPC分类号： H01L21/28 , H01L29/66 , H01L29/10 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28282 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/1037 , H01L29/1083 , H01L29/42332 , H01L29/42348 , H01L29/66537 , H01L29/7887 , H01L29/7923
摘要： Memory cells having split charge storage nodes and methods for fabricating memory cells having split charge storage nodes are disclosed. A disclosed method includes forming a first trench and an adjacent second trench in a semiconductor substrate, the first trench and the second trench each defining a first sidewall and a second sidewall respectively and forming a first source/drain region in the substrate and a second source/drain region in the substrate, where the first source/drain region and the second source/drain region are formed substantially under the first trench and the second trench in the semiconductor substrate respectively. Moreover, a method includes forming a bit line punch through barrier in the substrate between the first source/drain region and the second source drain region and forming a first storage element on the first sidewall of the first trench and a second storage element on the second sidewall of the second element. A word line is formed in contact with the first storage element and the second storage element.
摘要翻译：公开了具有分割电荷存储节点的存储单元和用于制造具有分离电荷存储节点的存储单元的方法。所公开的方法包括在半导体衬底中形成第一沟槽和相邻的第二沟槽，第一沟槽和第二沟槽分别限定第一侧壁和第二侧壁，并在衬底中形成第一源极/漏极区域，第二源极 /漏极区域，其中第一源极/漏极区域和第二源极/漏极区域分别基本上形成在半导体衬底中的第一沟槽和第二沟槽下方。此外，一种方法包括在第一源极/漏极区域和第二源极漏极区域之间的衬底中形成位线穿通阻挡层，并在第一沟槽的第一侧壁上形成第一存储元件，在第二沟槽的第二沟槽上形成第二存储元件第二元件的侧壁。形成与第一存储元件和第二存储元件接触的字线。

43. 发明授权

US08658496B2 Etch stop layer for memory cell reliability improvement 有权
标题翻译：蚀刻停止层，提高记忆体的可靠性
公开(公告)号：US08658496B2
公开(公告)日：2014-02-25
申请号：US13617291
申请日：2012-09-14
申请人： Hiroyuki Kinoshita , Angela Hui , Hsiao-Han Thio , Kuo-Tung Chang , Minh Van Ngo , Hiroyuki Ogawa
发明人： Hiroyuki Kinoshita , Angela Hui , Hsiao-Han Thio , Kuo-Tung Chang , Minh Van Ngo , Hiroyuki Ogawa
IPC分类号： H01L21/336
CPC分类号： H01L21/0217 , H01L21/28273 , H01L29/66825 , H01L29/7881
摘要： A memory device and a method of making the memory device are provided. A first dielectric layer is formed on a substrate, a floating gate is formed on the first dielectric layer, a second dielectric layer is formed on the floating gate, a control gate is formed on the second dielectric layer, and at least one film, including a conformal film, is formed over a surface of the memory device.
摘要翻译：提供存储器件和制造存储器件的方法。在基板上形成第一电介质层，在第一电介质层上形成浮栅，在浮栅上形成第二电介质层，在第二电介质层上形成控制栅，还包括至少一层，保形膜形成在存储器件的表面上。

44. 发明授权

US08603890B2 Air gap isolation in non-volatile memory 有权
标题翻译：非易失性存储器中的气隙隔离
公开(公告)号：US08603890B2
公开(公告)日：2013-12-10
申请号：US13162475
申请日：2011-06-16
申请人： Vinod Robert Purayath , George Matamis , Eli Harari , Hiroyuki Kinoshita , Tuan Pham
发明人： Vinod Robert Purayath , George Matamis , Eli Harari , Hiroyuki Kinoshita , Tuan Pham
IPC分类号： H01L21/76
CPC分类号： H01L21/764 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation between adjacent active areas of a substrate can be provided, at least in part, by bit line air gaps that are elongated in a column direction between the active areas. At least one cap is formed over each isolation region, at least partially overlying air to provide an upper endpoint for the corresponding air gap. The caps may be formed at least partially along the sidewalls of adjacent charge storage regions. In various embodiments, selective growth processes are used to form capping strips over the isolation regions to define the air gaps. Word line air gaps that are elongated in a row direction between adjacent rows of storage elements are also provided.
摘要翻译：提供了非易失性存储器阵列中的气隙隔离和相关制造工艺。至少部分地可以通过在活动区域之间沿列方向延伸的位线空气间隙来提供衬底的相邻有源区域之间的电隔离。在每个隔离区域上形成至少一个盖，至少部分地覆盖空气以提供相应气隙的上端点。帽可以至少部分地沿着相邻的电荷存储区域的侧壁形成。在各种实施方案中，选择性生长过程用于在隔离区域上形成封盖条以限定气隙。还提供了在相邻行存储元件之间沿行方向延伸的字线气隙。

45. 发明授权

US08598645B2 System and method for improving mesa width in a semiconductor device 有权
标题翻译：用于改善半导体器件中的台面宽度的系统和方法
公开(公告)号：US08598645B2
公开(公告)日：2013-12-03
申请号：US12910331
申请日：2010-10-22
申请人： Unsoon Kim , Angela T. Hui , Yider Wu , Kuo-Tung Chang , Hiroyuki Kinoshita
发明人： Unsoon Kim , Angela T. Hui , Yider Wu , Kuo-Tung Chang , Hiroyuki Kinoshita
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11521 , H01L27/11531
摘要： A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The nitride layer is trimmed on opposite sides of the trench to widen the trench within the nitride layer. The trench is filled with an oxide material. The nitride layer is stripped from the memory device, forming a mesa above the trench.
摘要翻译：提供了一种用于形成存储器件的方法。在衬底上形成氮化物层。蚀刻氮化物层和衬底以形成沟槽。在沟槽的相对侧上修整氮化物层，以加宽氮化物层内的沟槽。沟槽填充有氧化物材料。从存储器件剥离氮化物层，在沟槽上方形成台面。

46. 发明授权

US08564042B2 Dual storage node memory 有权
标题翻译：双存储节点存储器
公开(公告)号：US08564042B2
公开(公告)日：2013-10-22
申请号：US11702845
申请日：2007-02-05
申请人： Fred Cheung , Hiroyuki Kinoshita , Chungho Lee , Yu Sun , Chi Chang
发明人： Fred Cheung , Hiroyuki Kinoshita , Chungho Lee , Yu Sun , Chi Chang
IPC分类号： H01L29/94
CPC分类号： H01L29/66833 , G11C16/0475 , G11C16/3418 , G11C16/3427 , H01L27/115 , H01L27/11521
摘要： An embodiment of the present invention is directed to a memory cell. The memory cell includes a first charge storage element and a second charge storage element, wherein the first and second charge storage elements include nitrides. The memory cell further includes an insulating layer formed between the first and second charge storage elements. The insulating layer provides insulation between the first and second charge storage elements.
摘要翻译：本发明的实施例涉及存储单元。存储单元包括第一电荷存储元件和第二电荷存储元件，其中第一和第二电荷存储元件包括氮化物。存储单元还包括形成在第一和第二电荷存储元件之间的绝缘层。绝缘层提供第一和第二电荷存储元件之间的绝缘。

47. 发明授权

US08395677B2 Aberration correction apparatus, aberration correction method, and program 失效
标题翻译：畸变校正装置，像差校正方法和程序
公开(公告)号：US08395677B2
公开(公告)日：2013-03-12
申请号：US13226978
申请日：2011-09-07
申请人： Atsuo Kikuchi , Gentaro Irisawa , Atsuo Minato , Kenichi Nishio , Hyongmyong Kang , Hiroyuki Kinoshita , Tsukasa Hashino
发明人： Atsuo Kikuchi , Gentaro Irisawa , Atsuo Minato , Kenichi Nishio , Hyongmyong Kang , Hiroyuki Kinoshita , Tsukasa Hashino
IPC分类号： H04N5/228 , H04N9/73 , H04N5/262 , H04N9/64 , H04N9/74 , G06K9/00
CPC分类号： H04N9/045
摘要： An aberration correction apparatus includes: a correction data holding section that holds correction data on a correction level used to correct chromatic aberration of magnification; a center position discrepancy data holding section that holds center position discrepancy data on the discrepancy between the center of an image area and the position of an aberration center of the chromatic aberration of magnification; an aberration center calculating section that selects one of the center position discrepancy data that corresponds to a combination of the discrepancy variation conditions in an imaging apparatus and calculates the position of the aberration center based on the selected center position discrepancy data; an image height calculating section; a magnification chromatic aberration correction level calculating section; and a pixel value correcting section.
摘要翻译：像差校正装置包括：校正数据保持部，其保持用于校正倍率色像差的校正水平的校正数据; 中心位置偏差数据保持部分，其保持关于图像区域的中心与色像差的像差中心的位置之间的偏差的中心位置差异数据; 像差中心计算部分，选择与成像装置中的差异变化条件的组合相对应的中心位置差异数据之一，并基于所选择的中心位置差异数据计算像差中心的位置; 图像高度计算部; 倍率色像差校正电平计算部分; 和像素值校正部。

48. 发明申请

US20110309426A1 Metal Control Gate Structures And Air Gap Isolation In Non-Volatile Memory 有权
标题翻译：金属控制门结构和非易失性存储器中的空气间隙隔离
公开(公告)号：US20110309426A1
公开(公告)日：2011-12-22
申请号：US13163538
申请日：2011-06-17
申请人： Vinod Robert Purayath , Tuan Pham , Hiroyuki Kinoshita , Yuan Zhang , Henry Chin , James K. Kai , Takashi W. Orimoto , George Matamis , Henry Chien
发明人： Vinod Robert Purayath , Tuan Pham , Hiroyuki Kinoshita , Yuan Zhang , Henry Chin , James K. Kai , Takashi W. Orimoto , George Matamis , Henry Chien
IPC分类号： H01L29/788 , H01L21/336 , H01L21/764
CPC分类号： H01L27/11517 , H01L21/28273 , H01L21/764 , H01L21/7682 , H01L27/11519 , H01L27/11521 , H01L29/66825
摘要： High-density semiconductor memory utilizing metal control gate structures and air gap electrical isolation between discrete devices in these types of structures are provided. During gate formation and definition, etching the metal control gate layer(s) is separated from etching the charge storage layer to form protective sidewall spacers along the vertical sidewalls of the metal control gate layer(s). The sidewall spacers encapsulate the metal control gate layer(s) while etching the charge storage material to avoid contamination of the charge storage and tunnel dielectric materials. Electrical isolation is provided, at least in part, by air gaps that are formed in the row direction and/or air gaps that are formed in the column direction.
摘要翻译：提供了利用这些类型结构中的分立器件之间的金属控制栅极结构和气隙电隔离的高密度半导体存储器。在栅极形成和定义期间，蚀刻金属控制栅极层与蚀刻电荷存储层分离，以形成沿着金属控制栅极层的垂直侧壁的保护性侧壁间隔物。侧壁间隔物在蚀刻电荷存储材料时封装金属控制栅极层，以避免电荷存储和隧道介电材料的污染。至少部分地通过在行方向上形成的气隙和/或沿列方向形成的气隙提供电隔离。

49. 发明申请

US20110309425A1 Air Gap Isolation In Non-Volatile Memory 有权
标题翻译：非易失性存储器中的空气间隙隔离
公开(公告)号：US20110309425A1
公开(公告)日：2011-12-22
申请号：US13162475
申请日：2011-06-16
申请人： Vinod Robert Purayath , George Matamis , Eli Harari , Hiroyuki Kinoshita , Tuan Pham
发明人： Vinod Robert Purayath , George Matamis , Eli Harari , Hiroyuki Kinoshita , Tuan Pham
IPC分类号： H01L29/788 , H01L21/764
CPC分类号： H01L21/764 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： Air gap isolation in non-volatile memory arrays and related fabrication processes are provided. Electrical isolation between adjacent active areas of a substrate can be provided, at least in part, by bit line air gaps that are elongated in a column direction between the active areas. At least one cap is formed over each isolation region, at least partially overlying air to provide an upper endpoint for the corresponding air gap. The caps may be formed at least partially along the sidewalls of adjacent charge storage regions. In various embodiments, selective growth processes are used to form capping strips over the isolation regions to define the air gaps. Word line air gaps that are elongated in a row direction between adjacent rows of storage elements are also provided.
摘要翻译：提供了非易失性存储器阵列中的气隙隔离和相关制造工艺。至少部分地可以通过在活动区域之间沿列方向延伸的位线空气间隙来提供衬底的相邻有源区域之间的电隔离。在每个隔离区域上形成至少一个盖，至少部分地覆盖空气以提供相应气隙的上端点。帽可以至少部分地沿着相邻的电荷存储区域的侧壁形成。在各种实施方案中，选择性生长过程用于在隔离区域上形成封盖条以限定气隙。还提供了在相邻行存储元件之间沿行方向延伸的字线气隙。

50. 发明授权

US07842618B2 System and method for improving mesa width in a semiconductor device 有权
标题翻译：用于改善半导体器件中的台面宽度的系统和方法
公开(公告)号：US07842618B2
公开(公告)日：2010-11-30
申请号：US11193409
申请日：2005-08-01
申请人： Unsoon Kim , Angela T. Hui , Yider Wu , Kuo-Tung Chang , Hiroyuki Kinoshita
发明人： Unsoon Kim , Angela T. Hui , Yider Wu , Kuo-Tung Chang , Hiroyuki Kinoshita
IPC分类号： H01L21/302 , B44C1/22
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11521 , H01L27/11531
摘要： A method for forming a memory device is provided. A nitride layer is formed over a substrate. The nitride layer and the substrate are etched to form a trench. The nitride layer is trimmed on opposite sides of the trench to widen the trench within the nitride layer. The trench is filled with an oxide material. The nitride layer is stripped from the memory device, forming a mesa above the trench.
摘要翻译：提供了一种用于形成存储器件的方法。在衬底上形成氮化物层。蚀刻氮化物层和衬底以形成沟槽。在沟槽的相对侧上修整氮化物层，以加宽氮化物层内的沟槽。沟槽填充有氧化物材料。从存储器件剥离氮化物层，在沟槽上方形成台面。

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