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    • 47. 发明申请
    • Pedometer
    • 计步器
    • US20080243432A1
    • 2008-10-02
    • US12077661
    • 2008-03-20
    • Kazuo KatoAkira Takakura
    • Kazuo KatoAkira Takakura
    • G01C22/00
    • G01C22/006
    • It is made possible to reduce electric power consumption while suppressing an occurrence of a walking detection leak. By a cycle operation section and a cycle comparison section in a CPU, if it is judged that a walking signal from a detection circuit is within a predetermined cycle, the walking signal is counted as a step number by a step number count section. In a case where the walking signal within the predetermined cycle is not detected for a predetermined time by the cycle comparison section, a walking stop detection section judges to be a walking stop, an electric source control processing section controls an electric source control circuit to thereby switch the detection circuit to an intermittent drive from a continuous drive, and thereafter gradually prolongs a pause time of the intermittent drive for a predetermined time at a time in every time the walking signal within the predetermined cycle is not detected for the predetermined time.
    • 可以在抑制步行检测泄漏的发生的同时降低电力消耗。 通过CPU中的周期运算部和循环比较部,如果判断出来自检测电路的步行信号在规定的周期内,则步数信号由步数计数部计数为步数。 在循环比较部中,在规定时间内没有检测出规定的周期内的步行信号的情况下,步行停止检测部判断为行走停止,电源控制处理部控制电源控制电路 将检测电路从连续驱动器切换到间歇驱动,然后在预定时间内没有检测到在预定周期内的行走信号的每一次的时间,逐渐延长间歇驱动的暂停时间预定时间。
    • 50. 发明申请
    • Semiconductor integrated circuit having test function and manufacturing method
    • 具有测试功能和制造方法的半导体集成电路
    • US20060184848A1
    • 2006-08-17
    • US11335606
    • 2006-01-20
    • Mitsuo SerizawaKaname YamasakiMasafumi YamamotoKazuo Kato
    • Mitsuo SerizawaKaname YamasakiMasafumi YamamotoKazuo Kato
    • G01R31/28
    • G11C29/4401G01R31/318569G11C29/44G11C29/848G11C2029/0401G11C2029/0405G11C2029/3202
    • The logic integrated circuit comprises a logic circuit having the predetermined logic functions, a read/write memory circuit, a test circuit for testing whether fail bit is included in the memory circuit or not, and a boundary latch circuit formed of a plurality of flip-flop circuits which are capable of latching signals between said logic circuit and said memory circuit and also forming a shift register. Moreover, the logic integrated circuit is further provided with a fail relief information generating circuit for storing test result to the boundary latch circuit during execution of the test with the test circuit and generating the fail relief information for relieving fail of said memory circuit based on the stored test result. The test circuit mounted on the logic integrated circuit can generate the information for relieving fail bit in parallel with the test of a built-in memory circuit and can also output the same information to external side and relieve the RAM within a chip.
    • 逻辑集成电路包括具有预定逻辑功能的逻辑电路,读/写存储器电路,用于测试故障位是否包含在存储器电路中的测试电路,以及由多个触发器组成的边界锁存电路, 触发电路,其能够在所述逻辑电路和所述存储器电路之间锁存信号,并且还形成移位寄存器。 此外,逻辑集成电路还设置有故障补救信息生成电路,用于在与测试电路执行测试期间将测试结果存储到边界锁存电路,并且基于该测试电路产生用于缓解所述存储器电路的故障的故障排除信息 存储测试结果。 安装在逻辑集成电路上的测试电路可以生成与内置存储器电路的测试并行的解除故障位的信息,并且还可以向外部输出相同的信息并释放芯片内的RAM。