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    • 43. 发明授权
    • Semiconductor memory device and control method
    • 半导体存储器件及其控制方法
    • US06771552B2
    • 2004-08-03
    • US10372604
    • 2003-02-21
    • Hiroki Fujisawa
    • Hiroki Fujisawa
    • G11C700
    • G11C7/106G11C7/1051G11C7/1066G11C7/1072G11C7/1078G11C7/1087G11C11/4076G11C11/4093G11C2207/107
    • In a semiconductor memory device in which a system clock that is supplied from the outside and a data strobe signal that is received as input and supplied as output in synchronization with data are used to control operations for reading and writing data, the transmission of write data from FIFO memories to write amplifiers is controlled by the data strobe signal. In addition, switches for connecting write amplifiers with bit lines that are linked to memory cells that correspond to addresses to which write data are to be written are driven without delaying with respect to a timing signal that is synchronized with the system clock. Write data that have been received as burst input are transmitted in parallel from the FIFO memories to the write amplifiers in units of the prefetch number.
    • 在其中从外部提供的系统时钟和作为输入接收作为输出并与数据同步提供作为输出的数据选通信号的半导体存储器件被用于控制读取和写入数据的操作,写入数据的传输 从FIFO存储器到写放大器由数据选通信号控制。 此外,驱动与写入数据要被写入的地址相对应的与存储器单元链接的位线的写入放大器的开关相对于与系统时钟同步的定时信号而不会延迟。 以脉冲串输入接收的写入数据以预取数为单位从FIFO存储器并行发送到写入放大器。
    • 46. 发明授权
    • 3-deoxyglucosone production inhibitor
    • 3-脱氧葡萄糖酮生产抑制剂
    • US6040326A
    • 2000-03-21
    • US997872
    • 1997-12-24
    • Nigishi HottaHiroki Fujisawa
    • Nigishi HottaHiroki Fujisawa
    • C07D233/96A61K31/415A61K31/4166A61K31/417A61K31/4174A61P3/08A61P9/00A61P9/10A61P13/02A61P15/00A61P17/00A61P25/28A61P27/02A61P35/00A61P43/00
    • A61K31/4174A61K31/4166A61K31/417Y10S514/824
    • The production of 3-deoxyglucosone, which is an intermediate in the Maillard reaction and induces a crosslinking glycation of proteins participating in various diseases, is inhibited with an inhibitor containing at least one parabanic acid derivative as an effective ingredient. The at least one parabanic acid derivative is represented by the following formula (I) or a pharmaceutically acceptable salt thereof: ##STR1## wherein, R is hydrogen or lower alkyl; X is hydrogen, alkyl, cycloalkyl, lower alkylcycloalkyl, phenyl or phenylalkyl which is optionally substituted with lower alkyl, lower alkoxy, nitro and/or halogen; and n is an integer of from 1 to 4. Inhibiting the production of 3-DG, which is a highly active intermediate which participates in the formation of crosslinked protein in the Maillard reaction is useful for the treatment and the prevention of various diseases induced by deposition into tissues or sclerosis or denaturation of crosslinked protein, or diseases induced by aging and diabetic complications.
    • 使用含有至少一种对羟基苯甲酸衍生物作为有效成分的抑制剂抑制作为美拉德反应中的中间体并引起参与各种疾病的蛋白质的交联糖基化的3-脱氧葡萄糖酮的产生。 所述至少一种对羟基苯甲酸衍生物由下式(I)表示或其药学上可接受的盐:其中,R为氢或低级烷基; X是氢,烷基,环烷基,低级烷基环烷基,苯基或任选被低级烷基,低级烷氧基,硝基和/或卤素取代的苯基烷基; n为1〜4的整数。抑制在美拉德反应中参与交联蛋白质形成的高活性中间体的3-DG的制备可用于治疗和预防由 沉积到组织或硬化或交联蛋白质的变性,或由老化和糖尿病并发症引起的疾病。
    • 48. 发明授权
    • Semiconductor device having pull-up circuit and pull-down circuit
    • 具有上拉电路和下拉电路的半导体器件
    • US09041436B2
    • 2015-05-26
    • US13317696
    • 2011-10-26
    • Shunji KuwaharaHiroki Fujisawa
    • Shunji KuwaharaHiroki Fujisawa
    • H03K3/00G11C11/4074G11C5/06G11C7/10G11C11/4093
    • G11C11/4074G11C5/063G11C7/1057G11C11/4093Y10T307/50
    • To reduce power supply noises occurring in a control circuit unit for controlling an output buffer. A semiconductor device includes unit buffers for driving a data output terminal, impedance control circuits for controlling the unit buffers, and a control circuit unit for controlling the impedance control circuits. The impedance control circuits and the control circuit unit operate by mutually-different power supplies, the control circuit unit supplies pull-up data and pull-down data in mutually reverse phase to the impedance control circuits, and the impedance control circuits convert the pull-up data and the pull-down data from reverse phase to in-phase and supply the same to the unit buffers. Thereby, a noise is difficult to occur in a power supply VDD used for the control circuit unit.
    • 为了减少用于控制输出缓冲器的控制电路单元中发生的电源噪声。 半导体器件包括用于驱动数据输出端子的单元缓冲器,用于控制单元缓冲器的阻抗控制电路,以及用于控制阻抗控制电路的控制电路单元。 阻抗控制电路和控制电路单元通过相互不同的电源进行工作,控制电路单元向阻抗控制电路提供相互反相的上拉数据和下拉数据,并且阻抗控制电路将拉 - 并将下拉数据从反相到同相,并将其提供给单元缓冲器。 因此,在用于控制电路单元的电源VDD中难以发生噪声。